SLES211C February   2008  – July 2015 PCM1681 , PCM1681-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings: PCM1681
    3. 7.3 ESD Ratings: PCM1681-Q1
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Interface Timing Requirements
    8. 7.8 Typical Characteristics
      1. 7.8.1 Digital Filter (De-Emphasis Off)
      2. 7.8.2 De-Emphasis Filter
      3. 7.8.3 Analog Filter
      4. 7.8.4 Analog Dynamic Performance
        1. 7.8.4.1 Supply Voltage Characteristics
        2. 7.8.4.2 Temperature Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 System Clock Input
      2. 8.3.2 Power-on-Reset Function
      3. 8.3.3 Audio Serial Interface
      4. 8.3.4 Audio Data Formats and Timing
      5. 8.3.5 De-Emphasis Filter
      6. 8.3.6 Oversampling Rate Control
      7. 8.3.7 Zero Flag
      8. 8.3.8 Mode Control
        1. 8.3.8.1 Parallel Hardware Control
        2. 8.3.8.2 SPI Control Interface
        3. 8.3.8.3 Analog Outputs
          1. 8.3.8.3.1 VCOM Output
        4. 8.3.8.4 Register Write Operation
        5. 8.3.8.5 Interface Timing Requirements
    4. 8.4 Device Functional Modes
      1. 8.4.1 Control Modes
      2. 8.4.2 Audio Modes
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
        1. 8.5.1.1 Slave Address
        2. 8.5.1.2 Packet Protocol
        3. 8.5.1.3 Write Operation
        4. 8.5.1.4 Read Operation
      2. 8.5.2 Mode Control Registers
        1. 8.5.2.1 User-Programmable Mode Controls
    6. 8.6 Register Maps
      1. 8.6.1 Reserved Registers
      2. 8.6.2 Register Definitions
        1. 8.6.2.1  ATx[7:0]: Digital Attenuation Level Setting
        2. 8.6.2.2  MUTx: Soft Mute Control
        3. 8.6.2.3  DACx: DAC Operation Control
        4. 8.6.2.4  FLT: Digital Filter Roll-Off Control
        5. 8.6.2.5  FMT[3:0]: Audio Interface Data Format
        6. 8.6.2.6  SRST: Reset
        7. 8.6.2.7  ZREV: Zero-Flag Polarity Select
        8. 8.6.2.8  DREV: Output Phase Select
        9. 8.6.2.9  DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
        10. 8.6.2.10 DMC: Digital De-Emphasis All-Channel Function Control
        11. 8.6.2.11 REV[8:1]: Output Phase Select per Channel
        12. 8.6.2.12 OVER: Oversampling Rate Control
        13. 8.6.2.13 FLTx: Digital Filter Roll-Off Control per DATA Group
        14. 8.6.2.14 DAMS: Digital Attenuation Mode Select
        15. 8.6.2.15 AZRO[1:0]: Zero-Flag Channel-Combination Select
        16. 8.6.2.16 ZERO[8:1]: Zero-Detect Status (Read-Only, I2C Interface Only)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 D/A Output Filter Circuits
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Hardware Control Method
        2. 9.2.2.2 Audio Input
        3. 9.2.2.3 Audio Output
        4. 9.2.2.4 Master Clock
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Mechanical, Packaging, and Orderable Information

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