SLDS204B October 2014 – June 2020 PGA300
PRODUCTION DATA.
Figure 22 shows the EEPROM structure of the PGA300. The contents to program into the EEPROM must be transferred to the EEPROM cache before writes; that is, the EEPROM can only be programmed 8 bytes (one page) at a time. EEPROM reads occur without the EEPROM cache. For reading purposes the complete EEPROM is mapped to the address space from 0x00 to 0x7F in the control and status register page 5. Address 0x00 maps to EEPROM page 0, byte 0 and address 0x7F maps to EEPROM page 15, byte 7.