SCLS239N october   1995  – august 2023 SN54AHCT373 , SN74AHCT373

PRODMIX  

  1.   1
  2. 1Features
  3. 2Description
  4. 3Revision History
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements, VCC = 5 V ± 0.5 V
    7. 5.7 Switching Characteristics, VCC = 5 V ± 0.5 V
    8. 5.8 Noise Characteristics
    9. 5.9 Operating Characteristics
  7. 6Parameter Measurement Information
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  9. 8Device and Documentation Support
    1. 8.1 Documentation Support (Analog)
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • W|20
  • J|20
  • FK|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

The 'AHCT373 devices are octal-transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.

Device Information
PART NUMBER PACKAGE1 BODY SIZE2
SN54AHCT373 J (CDIP, 20) 24.2 mm × 6.92 mm
W (CFP, 20) 13.09 mm × 6.92 mm
FK (LCCC, 20) 8.89 mm × 8.89 mm
SN74AHCT373 DB (SSOP, 20) 7.20 mm × 5.30 mm
DW (SOIC, 20) 12.80 mm × 7.50 mm
NS (SOP, 20) 12.6 mm × 5.3 mm
N (PDIP, 20) 25.40 mm × 6.35 mm
PW (TSSOP, 20) 6.50 mm × 4.40 mm
GUID-3C867343-A070-439A-955B-A0ECF89BC256-low.gif Logic Diagram (Positive Logic)