SLLS961C July   2009  – June 2022 SN65HVDA195-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Local Interconnect Network (LIN) Bus
        1. 9.3.1.1 Transmitter Characteristics
        2. 9.3.1.2 Receiver Characteristics
      2. 9.3.2 Transmit Input (TXD)
      3. 9.3.3 Receive Output (RXD)
        1. 9.3.3.1 RXD Wake-Up Request
      4. 9.3.4 Supply Voltage (VSUP)
      5. 9.3.5 Ground (GND)
      6. 9.3.6 Enable Input (EN)
      7. 9.3.7 NWake Input (NWake)
      8. 9.3.8 Inhibit Output (INH)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Modes
      2. 9.4.2 Normal Mode
      3. 9.4.3 Sleep Mode
      4. 9.4.4 Wake-Up Events
      5. 9.4.5 Standby Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Typical Application
        1. 10.1.1.1 Design Requirements
        2. 10.1.1.2 Detailed Design Procedure
        3. 10.1.1.3 Application Curves
      2.      Power Supply Recommendations
      3. 10.1.2 Layout
        1. 10.1.2.1 Layout Guidelines
        2. 10.1.2.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

VSUP = 7 V to 27 V, TA = –40°C to 125°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
SUPPLY
Operational supply voltage(2)Device is operational beyond the LIN 2.0 defined nominal supply line voltage range of 7 V ≤ VSUP ≤ 18 V71427V
Nominal supply line voltageNormal and standby modes71418
Sleep mode71218
VSUP undervoltage threshold4.86
ISUPSupply currentNormal mode, EN = High, Bus dominant (total bus load where RLIN ≥ 500 Ω and CLIN ≤ 10 nF (see Figure 8-1)(3), INH = VSUP, NWake = VSUP1.27.5mA
Standby mode, EN = low, Bus dominant (total bus load where RLIN ≥ 500 Ω and CLIN ≤ 10 nF (see Figure 8-1)(3), INH = VSUP, NWake = VSUP12.1
Normal mode, EN = High, Bus recessive, LIN = VSUP, INH = VSUP, NWake = VSUP450775μA
Standby mode, EN = Low, Bus recessive, LIN = VSUP, INH = VSUP, NWake = VSUP450775
Sleep mode, EN = 0, TA = –40°C to 95°C,
7 V < VSUP ≤ 12 V, LIN = VSUP,
NWake = VSUP		1326
Sleep mode, EN = 0, TA = –40°C to 95°C,
12 V < VSUP < 18 V, LIN = VSUP,
NWake = VSUP		35
ΔISUPDelta supply current in sleep modeSleep mode, EN = 0, TA = –40°C to 95°C, Supply line voltage range of
7 V ≤ VSUP ≤ 18 V, LIN bus voltage: VSUP – 1.85 V ≤ LIN ≤ VSUP		20
RXD OUTPUT PIN
VOOutput voltage–0.35.5V
IOLLow-level output current, open drainLIN = 0 V, RXD = 0.4 V3.5mA
IIKGLeakage current, high-levelLIN = VSUP, RXD = 5 V–505μA
TXD INPUT PIN
VILLow-level input voltage–0.30.8V
VIHHigh-level input voltage25.5
VITInput threshold hysteresis voltage30500mV
Pulldown resistor125350800kΩ
IILLow-level input currentTXD = Low–505μA
LIN PIN (REFERENCED TO VSUP)
VOHHigh-level output voltageLIN recessive, TXD = High,
IO = 0 mA, VSUP = 14 V		VSUP – 1V
VOLLow-level output voltageLIN dominant, TXD = Low,
IO = 40 mA, VSUP = 14 V		00.2 × VSUP
RresponderPullup resistor to VSUPNormal and standby modes203060kΩ
Pullup current source to VSUPSleep mode, VSUP = 14 V, LIN = GND–2–20μA
ILLimiting currentTXD = 0 V45160220mA
TXD = 0 V, TA = –10°C to 125°C200
ILKGLeakage currentLIN = VSUP–505μA
ILKGLeakage current, loss of supply7 V < LIN ≤ 12 V, VSUP = GND5
12 V < LIN < 18 V, VSUP = GND10
VILLow-level input voltageLIN dominant0.4 × VSUPV
VIHHigh-level input voltageLIN recessive0.6 × VSUP
VITInput threshold voltage0.4 × VSUP0.5 × VSUP0.6 × VSUP
VhysHysteresis voltage0.05 × VSUP0.175 × VSUP
VILLow-level input voltage for wakeup0.4 × VSUP
EN PIN
VILLow-level input voltage–0.30.8V
VIHHigh-level input voltage25.5
VhysHysteresis voltage30500mV
Pulldown resistor125350800kΩ
IILLow-level input currentEN = Low–505μA
INH PIN
VoDC output voltage–0.3VSUP + 0.3V
RonOn state resistanceBetween VSUP and INH, INH = 2-mA drive, Normal or standby mode3585Ω
IIKGLeakage currentLow-power mode, 0 < INH < VSUP–505μA
NWAKE PIN
VILLow-level input voltage–0.3VSUP – 3.3V
VIHHigh-level input voltageVSUP – 1VSUP + 0.3
Pullup currentNWake = 0 V–45–10–2μA
IIKGLeakage currentVSUP = NWake–505
THERMAL SHUTDOWN
Shutdown junction thermal temperature190°C
AC CHARACTERISTICS
D1Duty cycle 1(4)THREC(max) = 0.744 × VSUP, THDOM(max) = 0.581 × VSUP,
VSUP = 7 V to 18 V,
tBIT = 50 μs (20 kbps),
D1 = tBus_rec(min)/ (2 × tBIT).
See Figure 7-1		0.396
D2Duty cycle 2(4)THREC(min) = 0.422 × VSUP, THDOM(min) = 0.284 × VSUP,
VSUP = 7.6 V to 18 V,
tBIT = 50 μs (20 kbps),
D2 = tBus_rec(max)/ (2 × tBIT).
See Figure 7-1		0.581
D3Duty cycle 3(4)THREC(max) = 0.778 × VSUP, THDOM(max) = 0.616 × VSUP,
VSUP = 7 V to 18 V,
tBIT = 96 μs (10.4 kbps),
D3 = tBus_rec(min)/ (2 × tBIT).
See Figure 7-1		0.417
D4Duty cycle 4(4)THREC(min) = 0.389 × VSUP, THDOM(min) = 0.251 × VSUP,
VSUP = 7.6 V to 18 V,
tBIT = 96 μs (10.4 kbps),
D4 = tBus_rec(max)/ (2 × tBIT).
See Figure 7-1		0.59
trx_pdrReceiver rising propagation delay timeRRXD = 2.4 kΩ, CRXD = 20 pF
See Figure 7-2
See Figure 8-1		6μs
trx_pdfReceiver falling propagation delay timeRRXD = 2.4 kΩ, CRXD = 20 pF
See Figure 7-2
See Figure 8-1		6
trx_symSymmetry of receiver propagation delay timerising edge with respect to falling edge (trx_sym = trx_pdf – trx_pdr)
RRXD = 2.4 kΩ, CRXD = 20 pF
See Figure 7-2
See Figure 8-1		–22
tNWakeNWake filter time for local wakeupSee Figure 9-42550150
tLINBUSLIN wake-up filter time (dominant time for wakeup through LIN bus)See Figure 9-32550150
tgo_to_operateSee Figure 9-2 to Figure 9-30.51
(1) Typical values are given for VSUP = 14 V at 25°C, except for low power mode where typical values are given for VSUP = 12 V at 25°C.
(2) All voltages are defined with respect to ground; positive currents flow into the SN65HVDA195 device.
(3) In the dominant state, the supply current increases as the supply voltage increases due to the integrated LIN responder termination resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the LIN responder termination is 20 kΩ, so the maximum supply current attributed to the termination is:
ISUP (dom) max termination ≉ (VSUP – (VLIN_Dominant + 0.7 V) / 20 kΩ
(4) Duty cycles: LIN driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 10 nF, 500 Ω. Duty cycles 3 and 4 are defined for 10.4-kbps operation. The SN65HVDA195 also meets these lower data rate requirements, while it is capable of the higher speed 20-kbps operation as specified by Duty cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle definitions, for details see the SAEJ2602 specification.
GUID-CD084EDA-78D6-4E82-9C9D-A8F08A9F58E8-low.gifFigure 7-1 Definition of Bus Timing Parameters
GUID-4EE08D77-4027-4642-A5B2-4A552340E9BA-low.gifFigure 7-2 Propagation Delay