SLLS992B August   2009  – March 2015 SN65LVDS93A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TTL Input Data
      2. 9.3.2 LVDS Output Data
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Edge
      2. 9.4.2 Low Power Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Power
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Signal Connectivity
        2. 10.2.2.2 PCB Routing
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Stackup
      2. 12.1.2 Power and Ground Planes
      3. 12.1.3 Traces, Vias, and Other PCB Components
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DGG Package
56-Pin TSSOP
(Top View)
SN65LVDS93A po_dgg_lls846.gif
ZQL Package
56-Ball BGA MICROSTAR
(Top View)
SN65LVDS93A po_zql_lls846.gif

Pin Functions - TSSOP

PIN I/O DESCRIPTION
NAME NO.
CLKSEL 17 I Selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input clock trigger
(CLKSEL = VIL).
CLKIN 31 I Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL.
CLKOUTM 40 O Differential LVDS pixel clock output.
Output is high-impedance when SHTDN is pulled low (de-asserted).
CLKOUTP 39 O
D0 51 I Data inputs; supports 1.8-V to 3.3-V input voltage selectable by VDD supply. To connect a graphic source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily intuitive).
Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23, and D27 to GND
D1 52
D2 54
D3 55
D4 56
D5 2
D6 3
D7 4
D8 6
D9 7
D10 8
D11 10
D12 11
D13 12
D14 14
D15 15
D16 16
D17 18
D18 19
D19 20
D20 22
D21 23
D22 24
D23 25
D24 27
D25 28
D26 30
D27 50
GND 5, 13, 21, 29, 33, 35, 36, 43, 49, 53 Power Supply(1) Supply Ground for VCC, IOVCC, LVDSVCC, and PLLVCC.
IOVCC 1, 26 I/O supply reference voltage (1.8 V up to 3.3 V matching the GPU data output signal swing)
LVDSVCC 44 3.3-V LVDS output analog supply
PLLVCC 34 3.3-V PLL analog supply
SHTDN 32 I Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and high (assert) for normal operation.
VCC 9 Power Supply(1) 3.3-V digital supply voltage
Y0M 48 O Differential LVDS data outputs.
Outputs are high-impedance when SHTDN is pulled low (de-asserted)
Y1M 46
Y2M 42
Y0P 47
Y1P 45
Y2P 41
Y3M 38 O Differential LVDS Data outputs.
Output is high-impedance when SHTDN is pulled low (de-asserted).
Note: if the application only requires 18-bit color, this output can be left open.
Y3P 37
(1) For a multilayer pcb, TI recommends keeping one common GND layer underneath the device and connecting all ground terminals directly to this plane.

Pin Functions - BGA MICROSTAR

BALL I/O DESCRIPTION
NAME NO.
CLKIN A2 CMOS IN with pulldn Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL.
CLKM D1 LVDS Out Differential LVDS pixel clock output.
Output is high-impedance when SHTDN is pulled low (de-asserted).
CLKP D2
CLKSEL D4 CMOS IN with pulldn Selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input clock trigger
(CLKSEL = VIL).
D0 J2 CMOS IN with pulldn Data inputs; supports 1.8-V to 3.3-V input voltage selectable by VDD supply. To connect a graphic source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily intuitive).
Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23, and D27 to GND.
D1 K1
D2 K2
D3 J3
D4 K3
D5 K4
D6 J4
D7 K5
D8 K6
D9 J6
D10 H4
D11 H6
D12 G5
D13 G6
D14 F6
D15 E5
D16 E6
D17 D6
D18 D5
D19 C6
D20 B6
D21 B5
D22 A6
D23 A5
D24 A4
D25 B4
D26 A3
D27 J1
GND A1, B1, C3, C5, F2, F5, J5, D3, G3, H3 Power Supply(1) Supply Ground for VCC, IOVCC, LVDSVCC, and PLLVCC.
IOVCC C4, G4 I/O supply reference voltage (1.8 V up to 3.3 V matching the GPU data output signal swing)
LVDSVCC F1 3.3-V LVDS output analog supply
PLLVCC B2 3.3-V PLL analog supply
SHTDN B3 CMOS IN with pulldn Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and high (assert) for normal operation.
VCC H5 Power Supply(1) 3.3-V digital supply voltage
Y0M H1 LVDS Out Differential LVDS data outputs.
Outputs are high-impedance when SHTDN is pulled low (de-asserted)
Y1M G1
Y2M E1
Y0P H2
Y1P G2
Y2P E2
Y3M C1 LVDS Out Differential LVDS Data outputs.
Output is high-impedance when SHTDN is pulled low (de-asserted).
Note: if the application only requires 18-bit color, this output can be left open.
Y3P C2
-- E3, E4, F3, F4 – Not connected
(1) For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane.