SLLS903A December   2009  – March 2024 SN65MLVD048

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Package Dissipation Ratings
    5. 5.5 Thermal Information
    6. 5.6 Device Electrical Characteristics
    7. 5.7 Receiver Electrical Characteristics
    8. 5.8 Receiver Switching Characteristics
    9. 5.9 Typical Characteristics
      1. 5.9.1 Eye Patterns
  7. 6 Parameter Measurement Information
  8. 7 Device Functional Modes
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Parameter Measurement Information

GUID-F781C960-62B3-4044-84FE-F7B88B96ACF3-low.gifFigure 6-1 Receiver Voltage and Current Definitions
Table 6-1 Type-1 Receiver Input Threshold Test Voltages
APPLIED VOLTAGESRESULTING DIFFERENTIAL INPUT VOLTAGERESULTING COMMON-MODE INPUT VOLTAGERECEIVER OUTPUT(1)
VIAVIBVIDVIC
2.4000.0002.4001.200H
0.0002.400–2.4001.200L
3.4003.3650.0353.3825H
3.3653.400–0.0353.3825L
–0.965–10.035–0.9825H
–1–0.965–0.035–0.9825L
(1) H= high level, L = low level, output state assumes receiver is enabled ( RE = L)
Table 6-2 Type-2 Receiver Input Threshold Test Voltages
APPLIED VOLTAGESRESULTING DIFFERENTIAL INPUT VOLTAGERESULTING COMMON-MODE INPUT VOLTAGERECEIVER OUTPUT(1)
VIAVIBVIDVIC
2.4000.0002.4001.200H
0.0002.400–2.4001.200L
3.4003.2650.1353.3325H
3.40003.3350.050653.3675L
–0.865–10.135–0.9325H
-0.935–10.065–0.9675L
(1) H= high level, L = low level, output state assumes receiver is enabled ( RE = L)
GUID-A52CF6D1-0C08-4730-B88C-305EA7D05D75-low.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, Frequency = 1MHz, duty cycle = 50 ± 5%. CL is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture capacitance within 2 cm of the D.U.T.
B. The measurement is made on test equipment with a –3dB bandwidth of at least 1GHz.
Figure 6-2 Receiver Timing Test Circuit and Waveforms
GUID-6002D55C-DDA4-494F-A614-9EB0897A9D66-low.gif
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1ns, frequency = 1MHz, duty cycle = 50 ± 5%.
B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T
C. CL is the instrumentation and fixture capacitance within 2 cm of the D.U.T. and ±20%. The measurement is made on test equipment with a –3dB bandwidth of at least 1GHz.
Figure 6-3 Receiver Enable/Disable Time Test Circuit and Waveforms
GUID-26EBDB96-837D-464F-873D-F41C24C666C2-low.gif
A. All input pulses are supplied by the Agilent 81250 Parallel BERT Stimulus System with plug-in E4832A.
B. The cycle-to-cycle jitter measurement is made on a TEK TDS6604 running TDSJIT3 application software.
C. All other jitter measurements are made with an Agilent Infiniium DCA-J 86100C Digital Communications Analyzer.
D. Period jitter and cycle-to-cycle jitter are measured using a 125MHz 50 ± 1% duty cycle clock input. Measured over 75K samples.
E. Deterministic jitter and random jitter are measured using a 250Mbps 215-1 PRBS input. Measured over BER = 10-12
Figure 6-4 Receiver Jitter Measurement Waveforms