SGDS010E September   1998  – May 2024 SN74AHC08Q-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Description
  4. 3Pin Configuration and Functions
  5. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    7. 4.7 Switching Characteristics, VCC = 5 V ± 0.5 V
    8. 4.8 Noise Characteristics
    9. 4.9 Operating Characteristics
  6. 5Parameter Measurement Information
  7. 6Detailed Description
    1. 6.1 Functional Block Diagram
    2. 6.2 Device Functional Modes
  8. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 Support Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • PW|14
  • BQA|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

This device is a quadruple 2-input positive-AND gate that performs the Boolean function Y + A • B or Y = A + B in positive logic.

Package Information
PART NUMBER PACKAGE#OL_VGY_SSG_4XB PACKAGE SIZE(1) BODY SIZE(2)
SN74AHC08Q-Q1 D (SOIC, 14) 8.65mm × 6mm 8.65mm × 3.9mm
PW (TSSOP, 14) 5.00mm × 6.4mm 5mm × 4.4mm
BQA (WQFN, 14) 3mm × 2.5mm 3mm × 2.5mm
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
SN74AHC08Q-Q1 Logic Diagram (Positive Logic)Logic Diagram (Positive Logic)