SCES503J NOVEMBER   2003  – June 2015 SN74AUP1G57

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, CL = 5 pF
    7. 6.7  Switching Characteristics, CL = 10 pF
    8. 6.8  Switching Characteristics, CL = 15 pF
    9. 6.9  Switching Characteristics, CL = 30 pF
    10. 6.10 Operating Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delays, Setup and Hold Times, and Pulse Duration
    2. 7.2 Enable and Disable Times
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Logic Configurations
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The AUP family is TI's premier solution to the low-power needs of the industry in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity, which produces very low undershoot and overshoot characteristics.

The SN74AUP1G57 features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and noninverter. All inputs can be connected to VCC or GND.

The device functions as an independent gate with Schmitt-trigger inputs, which allow for slow input transition and better switching noise immunity at the input.

NanoStar package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

8.2 Functional Block Diagram

SN74AUP1G57 ld_ces503.gif

8.3 Feature Description

This part is available in the TI NanoStar package. It has low static-power consumption with ICC = 0.9 μA maximum and low dynamic power consumption (Cpd = 4.3 pF, Typical at 3.3 V).

The inputs have low capacitance, with typical Ci = 1.5 pF.

This part has low noise, with overshoot and undershoot less than 10% of VCC.

This part supports partial-power-down mode operation. When this part is powered down (VCC = 0 V), the leakage current into the device is characterized by Ioff.

Schmitt-trigger inputs provide hysterisis and consistency in VIH / VIL.

It has a wide operating VCC range of 0.8 V to 3.6 V, and has been optimized for 3.3-V operation.

3.6-V I/O tolerant to support mixed-mode signal operation.

It has a low propagation delay of 5.3 ns at 3.3 V.

It is suitable for point-to-point applications.

8.4 Device Functional Modes

Table 1 lists all the functional modes of the SN74AUP1G57.

Table 1. Function Table

INPUTS OUTPUT
Y
In2 In1 In0
L L L H
L L H L
L H L H
L H H L
H L L L
H L H L
H H L H
H H H H

8.4.1 Logic Configurations

Table 2 lists all the logic functions of the SN74AUP1G57.

Table 2. Function Selection Table

LOGIC FUNCTION FIGURE NO.
2-input AND Figure 4
2-input AND with both inputs inverted Figure 7
2-input NAND with inverted input Figure 5, Figure 6
2-input OR with inverted input Figure 5, Figure 6
2-input NOR Figure 7
2-input NOR with both inputs inverted Figure 4
2-input XNOR Figure 8
SN74AUP1G57 lcon1_ces503.gifFigure 4. 2-Input AND Gate
SN74AUP1G57 lcon3_ces503.gifFigure 6. 2-Input NAND Gate With Inverted B Input
SN74AUP1G57 lcon5_ces503.gifFigure 8. 2-Input XNOR Gate
SN74AUP1G57 lcon2_ces503.gifFigure 5. 2-Input NAND Gate With Inverted A Input
SN74AUP1G57 lcon4_ces503.gifFigure 7. 2-Input NOR Gate