SCES517K December   2003  – November 2023 SN74AVC8T245

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, VCCA = 1.2 V
    7. 5.7  Switching Characteristics, VCCA = 1.5 V ± 0.1 V
    8. 5.8  Switching Characteristics, VCCA = 1.8 V ± 0.15 V
    9. 5.9  Switching Characteristics, VCCA = 2.5 V ± 0.2 V
    10. 5.10 Switching Characteristics, VCCA = 3.3 V ± 0.3 V
    11. 5.11 Operating Characteristics
    12. 5.12 Typical Total Static Power Consumption (ICCA + ICCB)
    13. 5.13 Typical Characteristics
  7.   Parameter Measurement Information
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Fully Configurable Dual-Rail Design
      2. 6.3.2 Support High-Speed Translation
      3. 6.3.3 Ioff Supports Partial-Power-Down Mode Operation
      4. 6.3.4 Balanced High-Drive CMOS Push-Pull Outputs
      5. 6.3.5 Vcc Isolation
    4. 6.4 Device Functional Modes
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGV|24
  • RHL|24
  • PW|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Control inputs VIH/VIL levels are referenced to VCCA voltage
  • VCC isolation feature – if either VCC input is at GND, all I/O ports are in the high-impedance state
  • Ioff supports partial power-down mode operation
  • Fully configurable dual-rail design allows each port to operate over the full 1.4-V to 3.6-V power-supply range
  • I/Os are 4.6-V tolerant
  • Maximum data rates:
    • 170Mbps (VCCA  < 1.8 V or VCCB  < 1.8 V)
    • 320Mbps (VCCA  ≥ 1.8 V and VCCB ≥ 1.8 V)