SCES131J March   1998  – April 2024 SN74LV126A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, VCC = 2.5V ±0.2V
    7. 5.7  Switching Characteristics, VCC = 3.3V ±0.3V
    8. 5.8  Switching Characteristics, VCC = 5V ±0.5V
    9. 5.9  Noise Characteristics
    10. 5.10 Operating Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • DB|14
  • DGV|14
  • PW|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SN74LV126A quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.

These quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.

The SN74LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

Package Information
PART NUMBERPACKAGE(1)PACKAGE SIZE(2)
SN74LV126AD (SOIC, 14)8.65mm × 6mm
NS (SOP, 14)10.2mm × 7.8mm
DB (SSOP, 14)6.2mm × 7.8mm
PW (TSSOP, 14)5mm × 6.4mm
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
GUID-692D1F5F-FB87-49DA-A6BA-DE90DB0CBD65-low.gif Logic Diagram (Positive Logic)