SNLS737 june   2023 SN75LVPE3410

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
  9. 8Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11.   Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Receiver Detect State Machine

The SN75LVPE3410 deploys an RX detect state machine that governs the RX detection cycle as defined in the PCI express specifications. At power up, after a manually triggered event through PWDN1 and PWDN2 pins (in pin mode), or writing to the relevant I2C / SMBus register, the redriver determines whether or not a valid PCI express termination is present at the far end of the link. The RX_DET pin of SN75LVPE3410 provides additional flexibility for system designers to appropriately set the device in the desired mode as provided in Table 7-3.

If all four channels of SN75LVPE3410 are used for same PCI express link, the PRWDN1 and PWDN2 pin can be shorted and driven together in a system (for example, by PCIE connector PRSNTx# or fundamental reset PERST# signal).

Table 7-3 Receiver Detect State Machine Settings
PWDN1 and PWDN2RXDETCOMMENTS
LL0PCI Express RX detection state machine is enabled. RX detection is asserted after 2x valid detections.
Pre Detect: Hi-Z, Post Detect: 50 Ω.
LL1PCI Express RX detection state machine is enabled. RX detection is asserted after 3x valid detections.
Pre Detect: Hi-Z, Post Detect: 50 Ω.
LL2 (Float)PCI Express RX detection state machine is enabled. RX detection is asserted after 1x valid detection.
Pre Detect: Hi-Z, Post Detect: 50 Ω.
LL3PCI Express RX detection state machine is disabled.
Recommended for non PCI Express interface use case where the SN75LVPE3410 is used as buffer with equalization.
Always 50 Ω.
HXManual reset, input is high impedance.