SNLS737 june   2023 SN75LVPE3410

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Characteristics
    8. 6.8 Typical Characteristics
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
  9. 8Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11.   Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.1.2 SMBUS/I2C Register Control Interface

If EN_SMB = L3 (SMBus / I2C control mode), the SN75LVPE3410 is configured through a standard I2C or SMBus interface that may operate up to 400 kHz. The target address of the SN75LVPE3410 is determined by the pin strap settings on the EQ1_ADDR1 and EQ0_ADDR0 pins. The device can be configured for best signal integrity and power settings in the system using the I2C or SMBus interface. The sixteen possible target addresses (8-bit) for the SN75LVPE3410 are provided in Table 7-5.

Table 7-5 SMBUS/I2C Target Address Settings
EQ1_ADDR1 PIN LEVELEQ0_ADDR0 PIN LEVEL8-BIT WRITE ADDRESS (HEX)7-BIT ADDRESS (HEX)
L0L00x300x18
L0L10x320x19
L0L20x340x1A
L0L30x360x1B
L1L00x380x1C
L1L10x3A0x1D
L1L20x3C0x1E
L1L30x3E0x1F
L2L00x400x20
L2L10x420x21
L2L20x440x22
L2L30x460x23
L3L00x480x24
L3L10x4A0x25
L3L20x4C0x26
L3L30x4E0x27