SLAS844A May   2012  – January 2016 TAS5624A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Electrical Characteristics - Audio Specification Stereo (BTL)
    7. 7.7 Electrical Characteristics - Audio Specification 4 Channels (SE)
    8. 7.8 Electrical Characteristics - Audio Specification Mono (PBTL)
    9. 7.9 Typical Characteristics
      1. 7.9.1 BTL Configuration
      2. 7.9.2 SE Configuration
      3. 7.9.3 PBTL Configuration
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  System Power-Up and Power-Down Sequence
        1. 9.3.1.1 Powering Up
        2. 9.3.1.2 Powering Down
      2. 9.3.2  Start-Up and Shutdown Ramp Sequence
      3. 9.3.3  Unused Output Channels
      4. 9.3.4  Device Protection System
      5. 9.3.5  Pin-to-Pin Short-Circuit Protection (PPSC)
      6. 9.3.6  Overtemperature Protection
      7. 9.3.7  Overtemperature Warning, OTW
      8. 9.3.8  Undervoltage Protection (UVP) and Power-On Reset (POR)
      9. 9.3.9  Error Reporting
      10. 9.3.10 Fault Handling
      11. 9.3.11 Device Reset
      12. 9.3.12 System Design Consideration
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Typical BTL Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Pin Connections
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Typical SE Configuration
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 Typical PBTL Configuration
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
    2. 11.2 Boot Strap Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 PCB Material Recommendation
      2. 12.1.2 PVDD Capacitor Recommendation
      3. 12.1.3 Decoupling Capacitor Recommendation
      4. 12.1.4 Circuit Component and Printed-Circuit-Board Recommendation
        1. 12.1.4.1 Circuit Component Requirements
        2. 12.1.4.2 Printed-Circuit-Board Requirements
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Power Supply Recommendations

11.1 Power Supplies

To facilitate system design, the TAS5624A needs only a 12-V supply in addition to the (typical) 36-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, for example, the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.

To provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_X) and each full-bridge has separate power stage supply (PVDD_X) and gate supply (GVDD_X) pins. Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the same 12-V source, TI highly recommends separating GVDD_AB, GVDD_CD, and VDD on the printed-circuit-board (PCB) by RC filters (see Layout Example for details). These RC filters provide the recommended high-frequency isolation. Pay special attention to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors must be avoided.

Pay special attention to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each full-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X connection is decoupled with minimum 2x, 220-nF ceramic capacitors placed as close as possible to each supply pin. TI recommends following the PCB layout of the TAS5624A reference design. For additional information on recommended power supply and required components, see the application diagrams in this data sheet.

The 12-V supply must be from a low-noise, low-output-impedance voltage regulator. Likewise, the 36-V power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on reset circuit. Moreover, the TAS5624A is fully protected against erroneous power-stage turn on due to parasitic gate charging when power supplies are applied. Thus, voltage-supply ramp rates (dV/dt) are non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).

11.2 Boot Strap Supply

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 300 kHz to 400 kHz, TI recommends using 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle.