SLOS946A May   2016  – December 2016 TAS5722L

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adjustable I2C Address
      2. 7.3.2 I2C Interface
        1. 7.3.2.1 Writing to the I2C Interface
        2. 7.3.2.2 Reading from the I2C Interface
      3. 7.3.3 Serial Audio Interface (SAIF)
        1. 7.3.3.1 Stereo I2S Format Timing
        2. 7.3.3.2 Stereo Left-Justified Format Timing
        3. 7.3.3.3 Stereo Right-Justified Format Timing
        4. 7.3.3.4 TDM Format Timing
      4. 7.3.4 Audio Signal Path
        1. 7.3.4.1 High-Pass Filter (HPF)
        2. 7.3.4.2 Amplifier Analog Gain and Digital Volume Control
        3. 7.3.4.3 Digital Clipper
        4. 7.3.4.4 Class-D Amplifier Settings
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SDZ)
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Mode Timing
      4. 7.4.4 Auto Sleep Mode
      5. 7.4.5 Active Mode
      6. 7.4.6 Mute Mode
      7. 7.4.7 Faults and Status
    5. 7.5 Register Maps
      1. 7.5.1 I2C Register Map Summary
      2. 7.5.2 Register Maps
        1. 7.5.2.1  Device Identification Register (0x00)
        2. 7.5.2.2  Power Control Register (0x01)
        3. 7.5.2.3  Digital Control Register 1 (0x02)
        4. 7.5.2.4  Register Name (offset = ) [reset = ] or (address = ) [reset = ]
        5. 7.5.2.5  Volume Control Register (0x04)
        6. 7.5.2.6  Analog Control Register (0x06)
        7. 7.5.2.7  Fault Configuration and Error Status Register (0x08)
        8. 7.5.2.8  Digital Clipper 2 Register (0x10)
        9. 7.5.2.9  Digital Clipper 1 Register (0x11)
        10. 7.5.2.10 Digital Control Register 3 (0x13)
        11. 7.5.2.11 Analog Control Register 2 (0x14)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Design Procedure
        1. 8.2.2.1 Overview
        2. 8.2.2.2 Select the PWM Frequency
        3. 8.2.2.3 Select the Amplifier Gain and Digital Volume Control
        4. 8.2.2.4 Select Input Capacitance
        5. 8.2.2.5 Select Decoupling Capacitors
        6. 8.2.2.6 Select Bootstrap Capacitors
      3. 8.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RSM PACKAGE
32 PINS
(TOP VIEW)
TAS5722L slos937_pin_out_tas5722l.gif

Pin Functions(2)

PIN I/O/P(1) DESCRIPTION
NAME NO.
ADR1 12 I I2C address inputs. Each pin can detect a short to DVDD, a short to GND, a 22-kΩ connection to GND and a 22-kΩ connection to DVDD.
ADR0 13 I
AVDD 28 P Analog power supply input. Connect directly to PVDD.
BCLK 6 I TDM Interface serial bit clock.
BST_N 18 P Class-D Amplifier negative bootstrap. Connect a capacitor between BST_N and OUT_N.
BST_P 23 P Class-D Amplifier positive bootstrap. Connect a capacitor between BST_P and OUT_P.
DVDD 11 P Digital power supply. Connect to 1.8-V supply with external decoupling capacitor.
FAULTZ 2 O Open drain active low fault flag. Pull up on PCB with resistor to DVDD.
GND 10 P Ground. Connect to PCB ground plane.
29
GVDD 30 O Class-D amplifier gate drive regulator output. Connect decoupling cap to PCB ground plane.
LRCLK 4 I TDM interface left/right clock.
MCLK 5 I Device master clock.
PGND 19 P Power ground. Connect to PCB ground plane.
20
21
22
PVDD 14 P Class-D amplifier power supply input. Connect to PVDD supply and decouple externally.
15
26
27
OUT_N 16 O Class-D amplifier negative output.
17
OUT_P 24 O Class-D amplifier positive output.
25
SCL 8 I I2C clock Input. Pull up on PCB with a 2.4-kΩ resistor.
SDA 9 I/O I2C bi-directional data. Pull up on PCB with a 2.4-kΩ resistor.
SDI 7 I TDM interface data input.
SDZ 3 I Active low shutdown signal. Assert low to hold device inactive.
VCOM 32 O Common mode reference output. Connect decoupling capacitor to the VREF_N pin.
VREF_N 1 P Negative reference for analog. Connect to VCOM and VREG capacitor negative pins.
VREG 31 O Analog regulator output. Connect decoupling capacitor to the VREF_N pin.
(1) I = input, O = output, P = power, I/O = bi-directional
(2) Connect exposed thermal pad to PCB ground plane