SLLSF19 December   2017 TCAN4420

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Power Supply Characteristics
    7. 6.7 AC and DC Electrical Characteristics
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 TXD Dominant Time Out (DTO)
      2. 8.3.2 CAN Bus Short Circuit Current Limiting
      3. 8.3.3 Thermal Shutdown
      4. 8.3.4 Under Voltage Lockout (UVLO) and Unpowered Device
        1. 8.3.4.1 VIO Supply PIN
    4. 8.4 Device Functional Modes
      1. 8.4.1 Polarity Configuration
      2. 8.4.2 Normal Polarity Mode
      3. 8.4.3 Reverse Polarity Mode
      4. 8.4.4 Driver and Receiver Function
      5. 8.4.5 Floating Terminals
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Bus Loading, Length and Number of Nodes
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 CAN Termination
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1 Layout Guidelines

  • Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and noise from propagating onto the board. In this layout example a transient voltage suppression (TVS) device, D1, has been used for added protection. The production solution can be either bi-directional TVS diode or varistor with ratings matching the application requirements. This example also shows optional bus filter capacitors C3 and C4. Additionally (not shown) a series common mode choke (CMC) can be placed on the CANH and CANL lines between the TCAN4420 transceiver and connector J1.
  • Design the bus protection components in the direction of the signal path. Do not force the transient current to divert from the signal path to reach the protection device.
  • Use supply (VCC) and ground planes to provide low inductance.

    • NOTE

    High-frequency currents follows the path of least impedance and not the path of least resistance.

  • Use at least two vias for supply (VCC) and ground connections of bypass capacitors and protection devices to minimize trace and via inductance.
  • Bypass capacitors should be placed as close as possible to the supply terminals of transceiver, examples are C1 on the VCC supply and C5 on the VIO supply.
  • Bus termination: this layout example shows split termination. This is where the termination is split into two resistors, R6 and R7, with the center or split tap of the termination connected to ground via capacitor C2. Split termination provides common mode filtering for the bus. When bus termination is placed on the board instead of directly on the bus, additional care must be taken to ensure the terminating node is not removed from the bus thus also removing the termination. See the application section for information on power ratings needed for the termination resistor(s).
  • To limit current of digital lines, serial resistors may be used. Examples are R2, R3, and R4. These are not required.
  • Pin 1: R1 is shown optionally for the TXD input of the device. If an open drain host processor is used, this is mandatory to ensure the bit timing into the device is met.
  • Pin 5: A bypass capacitor should be placed as close to the pin as possible (example C5). A voltage must be applied to the VIO for normal operation.
  • Pin 8: is shows the SW terminal with R4 and R5 as optional resistors. The SW terminal can also be tied to an IO for soft polarity configuration.