SNAS854 February   2023 TDC1000-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information (1)
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmitter Signal Path
      2. 8.3.2 Receiver Signal Path
      3. 8.3.3 Low Noise Amplifier (LNA)
      4. 8.3.4 Programmable Gain Amplifier (PGA)
      5. 8.3.5 Receiver Filters
      6. 8.3.6 Comparators for STOP Pulse Generation
        1. 8.3.6.1 Threshold Detector and DAC
        2. 8.3.6.2 Zero-Cross Detect Comparator
        3. 8.3.6.3 Event Manager
      7. 8.3.7 Common-Mode Buffer (VCOM)
      8. 8.3.8 Temperature Sensor
        1. 8.3.8.1 Temperature Measurement With Multiple RTDs
        2. 8.3.8.2 Temperature Measurement With a Single RTD
    4. 8.4 Device Functional Modes
      1. 8.4.1 Time-of-Flight Measurement Mode
        1. 8.4.1.1 Mode 0
        2. 8.4.1.2 Mode 1
        3. 8.4.1.3 Mode 2
      2. 8.4.2 State Machine
      3. 8.4.3 TRANSMIT Operation
        1. 8.4.3.1 Transmission Pulse Count
        2. 8.4.3.2 TX 180° Pulse Shift
        3. 8.4.3.3 Transmitter Damping
      4. 8.4.4 RECEIVE Operation
        1. 8.4.4.1 Single Echo Receive Mode
        2. 8.4.4.2 Multiple Echo Receive Mode
      5. 8.4.5 Timing
        1. 8.4.5.1 Timing Control and Frequency Scaling (CLKIN)
        2. 8.4.5.2 TX/RX Measurement Sequencing and Timing
      6. 8.4.6 Time-of-Flight (TOF) Control
        1. 8.4.6.1 Short TOF Measurement
        2. 8.4.6.2 Standard TOF Measurement
        3. 8.4.6.3 Standard TOF Measurement With Power Blanking
        4. 8.4.6.4 Common-Mode Reference Settling Time
        5. 8.4.6.5 TOF Measurement Interval
      7. 8.4.7 Averaging and Channel Selection
      8. 8.4.8 Error Reporting
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
        1. 8.5.1.1 Chip Select Bar (CSB)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Serial Data Input (SDI)
        4. 8.5.1.4 Serial Data Output (SDO)
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Level and Fluid Identification Measurements
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Level Measurements
          2. 9.2.1.2.2 Fluid Identification
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Water Flow Metering
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Regulations and Accuracy
          2. 9.2.2.2.2 Transit-Time in Ultrasonic Flow Meters
          3. 9.2.2.2.3 ΔTOF Accuracy Requirement Calculation
          4. 9.2.2.2.4 Operation
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6 Register Maps

Note:
  • Reserved bits must be written to 0 unless otherwise indicated.
  • Read-back value of reserved bits and registers is unspecified and should be discarded.
  • Recommended values must be programmed and forbidden values must not be programmed where they are indicated to avoid unexpected results.

8.6.1 TDC1000-Q1 Registers

#GUID-D52B58BA-FB8F-40CD-9790-27F8DD119B14/SNAS648182 lists the memory-mapped registers for the TDC1000-Q1. All register addresses not listed in #GUID-D52B58BA-FB8F-40CD-9790-27F8DD119B14/SNAS648182 should be considered as reserved locations and the register contents should not be modified.

Table 8-4 TDC1000-Q1 Registers
Address (Hex) ACRONYM REGISTER NAME RESET VALUE SECTION
0h CONFIG_0 Config-0 45h See here
1h CONFIG_1 Config-1 40h See here
2h CONFIG_2 Config-2 0h See here
3h CONFIG_3 Config-3 3h See here
4h CONFIG_4 Config-4 1Fh See here
5h TOF_1 TOF-1 0h See here
6h TOF_0 TOF-0 0h See here
7h ERROR_FLAGS Error Flags 0h See here
8h TIMEOUT Timeout 19h See here
9h CLOCK_RATE Clock Rate 0h See here


8.6.2 CONFIG_0 Register (address = 0h) [reset = 45h]

Return to #GUID-D52B58BA-FB8F-40CD-9790-27F8DD119B14/SNAS648182.

Figure 8-27 CONFIG_0 Register
(MSB) 76543210 (LSB)
TX_FREQ_DIVNUM_TX
R/W-2hR/W-5h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 8-5 CONFIG_0 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
[7:5]TX_FREQ_DIV(1)R/W2h

Frequency divider for TX clock and T1

0h: Divide by 2

1h: Divide by 4

2h: Divide by 8 (default)

3h: Divide by 16

4h: Divide by 32

5h: Divide by 64

6h: Divide by 128

7h: Divide by 256

[4:0]NUM_TXR/W5h

Number of TX pulses in a burst, ranging from 0 to 31.

5h: 5 pulses (default)

(1) See Timing Control and Frequency Scaling (CLKIN) for the definition of the time period T1.

8.6.3 CONFIG_1 Register (address = 1h) [reset = 40h]

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Figure 8-28 CONFIG_1 Register
(MSB) 76543210 (LSB)
RESERVEDNUM_AVGNUM_RX
R/W-1hR/W-0hR/W-0h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 8-6 CONFIG_1 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
[7:6]RESERVEDR/W1h

1h: Reserved (default)

[5:3]NUM_AVGR/W0h

Number of measurement cycles to average in stopwatch/MCU

0h: 1 measurement cycle (default)

1h: 2 measurement cycles

2h: 4 measurement cycles

3h: 8 measurement cycles

4h: 16 measurement cycles

5h: 32 measurement cycles

6h: 64 measurement cycles

7h: 128 measurement cycles

[2:0]NUM_RXR/W0h

Number of expected receive events

0h: Do not count events (32 STOP pulses output) (default)

1h: 1 event (1 STOP pulse output)

2h: 2 events (2 STOP pulses output)

3h: 3 events (3 STOP pulses output)

4h: 4 events (4 STOP pulses output)

5h: 5 events (5 STOP pulses output)

6h: 6 events (6 STOP pulses output)

7h: 7 events (7 STOP pulses output)

8.6.4 CONFIG_2 Register (address = 2h) [reset = 0h]

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Figure 8-29 CONFIG_2 Register
(MSB) 76543210 (LSB)
VCOM_SELMEAS_MODEDAMPINGCH_SWPEXT_CHSELCH_SELTOF_MEAS_MODE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 8-7 CONFIG_2 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
[7]VCOM_SELR/W0h

Common-mode voltage reference control

0h: Internal (default)

1h: External

[6]MEAS_MODER/W0h

AFE measurement type

0h: Time-of-flight measurement (default)

1h: Temperature measurement

[5]DAMPINGR/W0h

TX burst damping

0h: Disable damping (default)

1h: Enable damping

[4]CH_SWPR/W0h

Automatic channel swap in Mode 2 of operation. The setting is ignored if EXT_CHSEL = 1.

0h: Disable automatic channel swap (default)

1h: Enable automatic channel swap

[3]EXT_CHSELR/W0h

External channel select by CHSEL pin

0h: Disable external channel select (default).

1h: Enable external channel select

EXT_CHSEL = 1 overrides the CH_SWP and CH_SEL settings.

[2]CH_SELR/W0hActive TX/RX channel pair.

0h: Channel 1 (default)

1h: Channel 2

See Time-of-Flight Measurement Mode for channel definitions. The setting is ignored if EXT_CHSEL = 1.

[1:0]TOF_MEAS_MODER/W0h

Time-of-flight measurement mode

0h: Mode 0 (default)

1h: Mode 1

2h: Mode 2

3h: Reserved

8.6.5 CONFIG_3 Register (address 3h) [reset = 3h]

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Figure 8-30 CONFIG_3 Register
(MSB) 76543210 (LSB)
RESERVEDTEMP_MODETEMP_RTD_SELTEMP_CLK_DIVBLANKINGECHO_QUAL_THLD
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-3h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 8-8 CONFIG_3 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
[7]RESERVEDR/W0h

0h: Reserved (default)

[6]TEMP_MODER/W0h

Temperature measurement channels

0h: Measure REF, RTD1 and RTD2 (default)

1h: Measure REF and RTD1

[5]TEMP_RTD_SELR/W0h

RTD type

0h: PT1000 (default)

1h: PT500

[4]TEMP_CLK_DIVR/W0h

Clock divider for temperature mode

0h: Divide by 8 (default)

1h: Use TX_FREQ_DIV

[3]BLANKINGR/W0h

Power blanking in standard TOF measurements. The blanking length is controlled with the TIMING_REG field (see Standard TOF Measurement With Power Blanking).

0h: Disable power blanking (default)

1h: Enable power blanking

[2:0]ECHO_QUAL_THLDR/W3h

Echo qualification DAC threshold level with respect to VCOM

0h: –35 mV

1h: –50 mV

2h: –75 mV

3h: –125 mV (default)

4h: –220 mV

5h: –410 mV

6h: –775 mV

7h: –1500 mV

8.6.6 CONFIG_4 Register (address = 4h) [reset = 1Fh]

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Figure 8-31 CONFIG_4 Register
(MSB) 76543210 (LSB)
RESERVEDRECEIVE_
MODE		TRIG_EDGE_
POLARITY		TX_PH_SHIFT_POS
R/W-0hR/W-0hR/W-0hR/W-1Fh
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 8-9 CONFIG_4 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
[7]RESERVEDR/W0h

0h: Reserved (default)

[6]RECEIVE_MODER/W0h

Receive echo mode

0h: Single echo (default)

1h: Multi echo

[5]TRIG_EDGE_POLARITYR/W0h

Trigger edge polarity

0h: Rising edge (default)

1h: Falling edge

[4:0]TX_PH_SHIFT_POSR/W1Fh

TX 180° pulse shift position, ranging from 0 to 31.

1Fh: Position 31 (default)

TI does not recommend setting TX_PH_SHIFT_POS to 0 or 1.

8.6.7 TOF_1 Register (address = 5h) [reset = 0h]

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Figure 8-32 TOF_1 Register
(MSB) 76543210 (LSB)
PGA_GAINPGA_CTRLLNA_CTRLLNA_FBTIMING_REG[9:8]
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 8-10 TOF_1 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
[7:5]PGA_GAINR/W0h

PGA gain

0h: 0 dB (default)

1h: 3 dB

2h: 6 dB

3h: 9 dB

4h: 12 dB

5h: 15 dB

6h: 18 dB

7h: 21 dB

[4]PGA_CTRLR/W0h

PGA control

0h: Active (default)

1h: Bypassed and powered off

[3]LNA_CTRLR/W0h

LNA control

0h: Active (default)

1h: Bypassed and powered off

[2]LNA_FBR/W0h

LNA feedback mode

0h: Capacitive feedback (default)

1h: Resistive feedback

[1:0]TIMING_REG[9:8]R/W0h

The 2 most significant bits of the TIMING_REG field (see Standard TOF Measurement and Standard TOF Measurement With Power Blanking)

0h: 0 (default)

8.6.8 TOF_0 Register (address = 6h) [reset = 0h]

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Figure 8-33 TOF_0 Register
(MSB) 76543210 (LSB)
TIMING_REG[7:0]
R/W-0h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 8-11 TOF_0 Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
[7:0]TIMING_REG[7:0]R/W0h

The 8 least significant bits of the TIMING_REG field (see Standard TOF Measurement and Standard TOF Measurement With Power Blanking)

0h: 0 (default)

8.6.9 ERROR_FLAGS Register (address = 7h) [reset = 0h]

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Figure 8-34 ERROR_FLAGS Register
7 (MSB)6543210 (LSB)
RESERVEDERR_
SIG_WEAK		ERR_NO_SIGERR_
SIG_HIGH
R-0hR-0hR/W1C-0R/W1C-0
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 8-12 ERROR_FLAGS Register Field Descriptions(1)(2)
BITFIELDTYPERESETDESCRIPTION
[7:3]RESERVEDR0h

0h: Reserved (default)

[2]ERR_SIG_WEAKR0h

1h: The number of received and qualified zero-crossings was less than the expected number set in NUM_RX field and a timeout occurred.

[1]ERR_NO_SIGR/W1C0h

1h: No signals were received and timeout occurred.

Writing a 1 to this field resets the state machine, halts active measurements and returns the device to the SLEEP or READY mode and resets the average counter and automatic channel selection in measurement Mode 2.

[0]ERR_SIG_HIGHR/W1C0h

1h: The received echo amplitude exceeds the largest echo qualification threshold at the input of the comparators. The error is only reported when ECHO_QUAL_THLD = 0x07.

Writing a 1 to this field will reset all the error flags and reset the ERRB pin to high.

(1) TI recommends to read the error status register or the ERRB pin before initiating a new measurement.
(2) All error flags should be cleared before initiating a new measurement.

8.6.10 TIMEOUT Register (address = 8h) [reset = 19h]

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Figure 8-35 TIMEOUT Register
(MSB) 76543210 (LSB)
RESERVEDFORCE_
SHORT_TOF		SHORT_TOF_BLANK_PERIODECHO_
TIMEOUT		TOF_TIMEOUT_CTRL
R/W-0hR/W-0hR/W-3hR/W-0hR/W-1h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 8-13 TIMEOUT Register Field Descriptions
BITFIELDTYPERESETDESCRIPTION
[7]RESERVEDR/W0h

0h: Reserved (default)

[6]FORCE_SHORT_TOFR/W0h

Short time-of-flight control

0h: Disabled (default)

1h: Force a short time-of-flight measurement

[5:3]SHORT_TOF_BLANK_PERIOD(1)R/W3h

Short time-of-flight blanking period (see Short TOF Measurement)

0h: 8 × T0

1h: 16 × T0

2h: 32 × T0

3h: 64 × T0 (default)

4h: 128 × T0

5h: 256 × T0

6h: 512 × T0

7h: 1024 × T0

[2]ECHO_TIMEOUTR/W0h

Echo receive timeout control (see TOF Measurement Interval)

0h: Enable echo timeout (default)

1h: Disable timeout

[1:0]TOF_TIMEOUT_CTRL(1)R/W1h

Echo listening window timeout (see TOF Measurement Interval)

0h: 128 × T0

1h: 256 × T0 (default)

2h: 512 × T0

3h: 1024 × T0

(1) See Timing Control and Frequency Scaling (CLKIN) for the definition of the time period T0.

8.6.11 CLOCK_RATE Register (address = 9h) [reset = 0h]

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Figure 8-36 CLOCK_RATE Register
(MSB) 76543210 (LSB)
RESERVEDCLOCKIN_DIVAUTOZERO_PERIOD
R/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read or write; R = Read only; R/W1C = Read or write 1 to clear
Table 8-14 CLOCK_RATE Register Field Descriptions(1)
BITFIELDTYPERESETDESCRIPTION
[7:3]RESERVEDR/W0h

0h: Reserved (default)

[2]CLOCKIN_DIV(1)R/W0h

CLKIN divider to generate T0

0h: Divide by 1 (default)

1h: Divide by 2

[1:0]AUTOZERO_PERIOD(1)R/W0h

Receiver auto-zero period

0h: 64 × T0 (default)

1h: 128 × T0

2h: 256 × T0

3h: 512 × T0

(1) See Timing Control and Frequency Scaling (CLKIN) for the definition of the time period T0.