SNLS747
November 2023
TDES4940
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device and Documentation Support
4.1
Documentation Support
4.1.1
Related Documentation
4.2
Support Resources
4.3
Trademarks
4.4
Electrostatic Discharge Caution
4.5
Glossary
5
Mechanical, Packaging, and Orderable Information
5.1
Package Option Addendum
5.2
Tape and Reel Information
Package Options
Mechanical Data (Package|Pins)
RUR|88
MPQF502A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snls747_oa
snls747_pm
1
Features
DisplayPort (DP) / Embedded DisplayPort (eDP) Transmitter
VESA DP v1.4a/eDP v1.4b transmitter
HBR3/HBR2/HBR/RBR Link Bit Rates
Main link: 1, 2, or 4 lanes
Each lane up to 8.1Gbps
AUX CH 1Mbps
Hot Plug Detect (HPD)
Extracts aggregated video streams to local eDP display
Designed for 4 K @ 60 Hz video resolution
Stream synchronization and splitting
V
3
Link enhanced video interface
13.5/12.528/10.8/6.75/3.375 Gbps per Channel; Up to 27 Gbps over dual channels
Coax/STP interconnect support
Selectable 1, 2 channels
Daisy-chain and splitting
Adaptive equalization
Ultra-low latency control channel
Two fast-mode plus I2C up to 1 MHz (up to 3.4 MHz local bus access)
High-speed GPIOs
Supports SPI and UART pass through GPIOs
Compatibility
Integrated HDCP v1.4 with on-chip keys
V
3
Link video and V
3
Link enhanced video product families
Image enhancement (white balance and dithering)
Security and diagnostics
Voltage and temperature monitoring
BIST and pattern generation
CRC and error diagnostics
ECC on control bits
Unique ID for counterfeit protection
Advanced link robustness and EMC control
Spread spectrum clocking generation (SSCG)
Adaptive Receiver Equalization (AEQ)
Low power operation
1.8V and 1.15V dual power supply
Qualifications
ISO 10605 and IEC 61000-4-2 ESD compliant
Temperature: -20°C to +85°C