SBOS758E May   2016  – May 2021 THS6212

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VS = 12 V
    6. 6.6 Electrical Characteristics: VS = 28 V
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics: VS = 12 V
    9. 6.9 Typical Characteristics: VS = 28 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage and Current Drive
      2. 7.3.2 Driving Capacitive Loads
      3. 7.3.3 Distortion Performance
      4. 7.3.4 Differential Noise Performance
      5. 7.3.5 DC Accuracy and Offset Control
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband Current-Feedback Operation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Dual-Supply Downstream Driver
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Line Driver Headroom Requirements
          2. 8.2.2.2.2 Computing Total Driver Power for Line-Driving Applications
    3. 8.3 What To Do and What Not to Do
      1. 8.3.1 What To Do
      2. 8.3.2 What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.2 Detailed Design Procedure

For ease of test purposes in this design, the THS6212 input impedance is set to 50 Ω with a resistor to ground and the output impedance is set to 50 Ω with a series output resistor. Voltage swings reported in the Electrical Characteristics tables are taken directly at the input and output pins, whereas load powers (dBm) are defined at a matched 50-Ω load. For the circuit of Figure 8-1, the total effective load is 100 Ω || 1.24 kΩ || 1.24 kΩ = 86.1 Ω. This approach allows a source termination impedance to be set at the input that is independent of the signal gain. For instance, simple differential filters can be included in the signal path right up to the noninverting inputs with no interaction with the gain setting. The differential signal gain for the circuit of Figure 8-1 is given by Equation 5:

Equation 5. GUID-301C1ABF-15DD-4BEC-85FB-F882DDD582C5-low.gif

where

  • AD = differential gain

A value of 274 Ω for the AD = 10-V/V design is given by Figure 8-1. The device bandwidth is primarily controlled with the feedback resistor value because the THS6212 is a current-feedback (CFB) amplifier; the differential gain, however, can be adjusted with considerable freedom using just the RG resistor. In fact, RG can be reduced by a reactive network that provides a very isolated shaping to the differential frequency response.

Various combinations of single-supply or ac-coupled gain can also be delivered using the basic circuit of Figure 8-1. Common-mode bias voltages on the two noninverting inputs pass on to the output with a gain of 1 V/V because an equal dc voltage at each inverting node does not create current through RG. This circuit does show a common-mode gain of 1 V/V from the input to output. The source connection must either remove this common-mode signal if undesired (using an input transformer can provide this function), or the common-mode voltage at the inputs can be used to set the output common-mode bias. If the low common-mode rejection of this circuit is a problem, the output interface can also be used to reject that common-mode signal. For instance, most modern differential input analog-to-digital converters (ADCs) reject common-mode signals very well, and a line-driver application through a transformer also attenuates the common-mode signal through to the line.