7.3.1 High Output Current Line Driver

The main purpose for the device is to provide a high output current into a heavy load. For the THS6226A, with its xDSL application targeted, the load is typically 100 Ω and currents as high as 400 mA are supported with excellent linearity. The core of the line driver is a class AB amplifier providing both good efficiency and high current drive capability. The high output line driver is the core of the device and any external circuit interface is located on both the device inputs and output.

7.3.2 Charge Pump

The class H functionality of the device is brought on by the integration of a charge pump. The charge pump is a power-supply function to the line driver. The role of the charge pump is to vary the power supply from (12 V / GND) to (20 V / –8 V) and allow the line driver to support high peak to average ratio (PAR) signals while minimizing power consumption and maintaining excellent linearity. The charge pump is controlled externally by the V_{H_EN} pin. A logic high on the V_{H_EN} pin results in the power supply of the class AB line driver going to (20 V / –8 V), while a logic low on the V_{H_EN} pin results in normal operation under the (12 V / GND) supplies.

7.3.3 Voltage Reference

An internal voltage reference provides the device common-mode input and output voltage.

7.3.4 Logic

The DATA and CLK pins allow access to the internal logic circuit implemented in the device. This logic circuit allows each channel to either be programmed individually for quiescent current, turn the charge pump on or off, disable the main amplifier, or select the line termination mode. For more information on programming, refer to the Programming section.

7.3.5 Active Impedance

The line driver incorporates the positive feedback path to provide the termination to the load. For the device, the synthesis factor implemented is 5.

7.3.6 RESET Pin

The RESET pin provides a quick and easy way to disable the two ports immediately if a fault condition on the line occurs.

7.5.1 Programming the Device

Programming the device is accomplished through a serial interface (pins 4 and 5) and proceeds in the following sequence:

• Two start bits are required (B0 = 0 followed by B1 = 1).
• B2 through B9 are used to program the device. (Table 1 lists the bit descriptions.)
• B10 (described in Table 2) is the parity bit that controls whether the word is loaded or not.
• B11 is the stop bit and must be set to B11 = 1.

Figure 32 shows the required sequence.

Figure 32. DATA Description

7.5.2 Quiescent Current

The device quiescent current is dissipated in two main device modules: the class AB and the charge pump. Bits B4 (PD1) and B5 (PD0) select one of the possible four modes of operation:

1. Class AB mode (charge pump disabled),
2. Class H mode (charge pump enabled),
3. Disable mode, or
4. Line termination mode (maintains line matching, core amplifier at very low bias mode and charge pump disabled for lowest power consumption possible).

Table 3 lists the details on each bit functionality and the approximate quiescent current. The various power modes are shown in Table 3. For all modes, when B6 through B9 are not defined, set B9 = B8 = B7 = B6 = 0 to achieve the lowest power dissipation possible.

The class AB quiescent current is set by bits B6 to B9, using B4 and B5 for the power-down function and B2 and B3 for channel selection. The approximate quiescent current for the amplifier core is shown in Table 4.

Channel selection is shown in Table 5. Each channel can be programmed independently, or together if both B2 and B3 are set to 1.

At startup, the internal register is set as shown in Figure 33.

In this condition, the total quiescent power dissipation is 10.2 mW per port on a +12-V supply.