Table 1. Result Transfer Format and Time Range

Table 2. Result-Interface Clock

Table 3. Counter Range

8.4.5.1 Preconditioning Holdoff Delay Time

The preconditioning circuitry controls the ON/OFF state of the event latches. Following a Sync input signal, the TMU checks for a number of conditions before it proceeds with the time-measurement operation. Event input signals are ignored until all arming conditions are met. These conditions are as follows:

The hold-off delay is a programmable delay used to inhibit the creation of the next timestamp until the hold-off delay has expired. A 16-bit register is used for the hold-off delay count register. One holdoff delay register exists for each of the four event input channels.

The generation of a timestamp reloads the value from the holdoff delay register into a down counting counter. Timestamp generation pauses until hold-off delay counter reaches zero. There are seven ranges for the holdoff delay maximum duration. Three register bits are used to specify the required range.

Table 4 defines these ranges.

In range 1 each count in the holdoff register delays the next possible timestamps by 10 ns (100-MHz clock period). The maximum delay range for this feature is 2.684 s for each channel. To disable this feature, a register bit (HOffTm_EN_x) is set to 0.

8.4.5.2 Arming Conditions

An additional arming condition for each event channel is based on other channels meeting some preprogrammed conditions before it can become fully armed. These conditions are in addition to the individual channel arming conditions.

• A given channel does not become fully armed until one, two, or all three of the other channels are armed. A logical AND of one or more channels.
• A given channel does not become fully armed until the holdoff delay expires, the arming counter reaches zero, and the logical OR of one or more channels has been active.

The following tables define this conditional operation.

Table 9. Control and Status Register Descriptions For All Channels (X)

Table 10. Control and Status Register Descriptions for All Channels (X)

Table 11. Central Control and Status Registers Description

8.5.1.1 Serial Interface

The TMU serial interface operates at speeds of up to 50 MHz. Register addresses are 8 bits long. Data words are 16 bits wide, enabling more-efficient interface transactions. The serial bus implementation uses three LVCMOS signals: HCLK, Hstrobe, and Hdata. The HCLK and Hstrobe signals are inputs only, and the Hdata signal is bidirectional. The HCLK signal is not required to run continuously. Thus, the host processor may disable the clock by setting it to a low state after the completion of any required register accesses.

When data is transferred into the device, Hdata is configured as an input bus, and data is latched on a rising edge of HCLK. When data is transferred out of the part, Hdata is configured as an output bus, and data is updated on the falling edge of HCLK. Hstrobe is the control signal that identifies the beginning of a host bus transaction. Hstrobe must remain low for the duration of the transaction, and must go high for at least two clock cycles before another transaction can begin.

8.5.1.2 Read vs Write Cycle

The first Hdata bit latched by HCLK in a transaction identifies the transaction type.
First Hdata bit = 1 for read; data flows out of the chip.
First Hdata bit = 0 for write; data flows into the chip.

8.5.1.3 Parallel (Broadcast) Write

Parallel write is a means of allowing identical data to be transferred to more than one channel in one transaction. The second Hdata bit of a transaction indicates whether a parallel write occurs.
Second Hdata bit = 0; data goes to the selected channel.
Second Hdata bit = 1; data goes to all four channels.

8.5.1.4 Address

After the R/W bit and the parallel write bit, the following 8 bits on the Hdata line contain the source address of the data word for a read cycle or the destination address of the data word for a write cycle. Address bits are shifted in MSB first, LSB last.
Third HCLK – Address Bit 7 (MSB)
Tenth HCLK – Address Bit 0 (LSB)

8.5.1.5 Data

The data stream is 16 bits long, and it is loaded or read back MSB first, LSB last. The timing for read and write cycles is different, as the drivers on Hdata alternate between going into high-impedance and driving the line.

8.5.1.6 Reset

Reset is an external hardware signal that places all internal registers and control lines into their default states. The THS788 device resets after a power-up sequence (POR). Hardware reset is an LVCMOS active-low signal and is required to stay low for approximately 100 ns.

Reset places the TMU in a predetermined idle state at power on, and anytime the system software initializes the system hardware. In the idle state, the TMU ignores state changes on the Event inputs and never creates timestamps. The TMU is capable of switching within 250 μs from the idle state to a state that creates accurate timestamps.

8.5.1.7 Chip ID

Address (83h) is a read-only register that identifies the product and the die revision. The 16-bit register is divided into two 8-bit sections. The LSB represents the revision history and the MSB represents the last two digits of THS788 device (i.e., 80). The first revision (1.0) is as follows:

1000 0000 0001.0000

8.5.1.8 Read Operations

Reading the THS788 device registers via the host interface requires the following sequence:

The host controller initiates a read cycle by setting the host strobe signal, Hstrobe, to a low state. The serial Hdata sequence starts with a high R/W bit, followed by (either 1 or 0) for parallel-write bit and 8 bits of address, with most-significant bit (A7) first. The host controller should put the Hdata signal in the high-impedance state beginning at the falling edge of HCLK pulse 10. The THS788 device allows one clock cycle, (r0) for the host to reverse the data-channel direction and begins driving the Hdata line on the falling edge of HCLK pulse 11. The data is read beginning with the most-significant bit (D15) and ending with the least-significant bit (D0).

The host must drive Hstrobe to a high state for a minimum of two HCLK periods beginning at the falling edge of HCLK pulse 27 to indicate the completion of the read cycle. Figure 3 shows the timing diagram of the read operation.

Figure 3. Read Operation

8.5.1.9 Write Operations

Writing into the THS788 device registers via the host interface requires the following sequence:

After the Hstrobe line is pulled low (start condition), the R/W bit is set low, followed by a 0 for the parallel-write bit (single-register write), then the memory address (A7–A0) followed by the data (D15:D0) to be programmed. The next clock cycle (w) is required to allow data to be latched and stored at the destination address (or addresses in the case of a parallel write), followed by at least two dummy clock cycles during which the Hstrobe is high, indicating the completion of the write cycle. Figure 4 and Figure 4 show timing diagrams of write operations.

Figure 4. Write Operation

8.5.1.10 Write Operations to Multiple Destinations

This is similar to the single-write operation except the parallel-load bit is set to 1.

Figure 5. Write Operations to Multiple Destinations

8.5.2.1 Event Latches

Each event channel and the sync channel include two event latches whose inputs are both connected to the LVDS input-buffer output. One latch is the time-measurement signal path and connects to the interpolator and synchronizer. The other latch connects to the preconditioning circuitry. A selectable rising or falling edge of an event pulse sets the latch. the latch remains set until the interpolator has finished processing the event, at which time the interpolator resets the latch. The latch, however, does not accept another event pulse until the event input returns to its initial state and remains for the initial event-pulse duration. Any event transitions which occur before the interpolator has completed processing the previous event are ignored. For example, assume that rising edge is selected. Two rising edges can occur as quickly as 5 ns apart. The falling edge can occur anywhere from 250 ps after the rising edge to 250 ps before the next rising edge. Any other edges or glitches are ignored. In addition to the rising/falling-edge selection, the event latch includes the gating function whereby the preconditioning logic controls whether the TMU accepts and processes an event input. The second event latch operates similarly to the main signal-path latch with the following exceptions: The latch is followed by and ECL-to-CMOS converter , because all the preconditioning logic is CMOS instead of the fast ECL circuitry in the measurement chain. The preconditioning logic rather than the interpolator resets this latch, and the timing of the reset pulse is slightly faster than the interpolator.

8.5.2.2 FIFO

Timestamps are written to a FIFO at high speed and read for further processing at a lower speed before being sent to the result interface. This FIFO is 15 bits deep and 40 bits wide. There are four FIFOs in THS788 device, one for each channel. There are two status registers (FIFO_Full_x and FIFO_Empty_x), which are set when a FIFO reaches its full capacity and when it is empty, respectively.

Timestamps are taken and loaded into the FIFO as events occur. Timestamps are mathematically processed by an arithmetic logic unit (ALU) which calculates the difference between the event and the sync timestamps and factors in the appropriate calibration value from the calibration register. The ALU operates on the data as it is read out of the FIFO and sent out through the serial-results interface. The serial-results interface controls the output of the FIFO.

8.5.2.3 Result-Interface Operation

The TMU initiates a read cycle by setting the strobe signal, Rstrobe, to a low state, indicating that the data transfer is about to begin. The serial Rdata sequence starts with a TAG bit, followed by the 40-bit data (R0 to R39). R39 (MSB) is the sign bit. Following the last data bit (R39), the strobe signal (Rstrobe) goes high for two clock cycles, indicating the end of the transaction.

The data is clocked out of the TMU on the rising edge of RCLK. The receiving device clocks the data in on the rising edge of RCLK. Figure 6 and Figure 7 show a 40-bit result on the result interface.

Figure 6. Result-Interface Operation A

Figure 7. Result-Interface Operation B

8.5.2.4 Serial Results Latency

The event stored in the FIFO will be transferred to ALU and subsequently to the free running results data shift register when the shift register enters a load pulse. The load pulse is generated once per ALU/shift register processing cycle. The load pulse will trigger the ALU and transfer result to the parallel to serial shift register for output. The cycle time of the load pulse is dependent upon the depth of the result transfer register and data rate. Because the results parallel to serial register are free running, the load pulse will be asynchronous to the actual event. So, the latency will depend upon where in the current cycle the load pulse occurred relative to the event being captured into the FIFO.

The worst case for data to be output from serial bus:

The best case for data to be output from serial bus:

In the case where R_CLK = 300 MHz, with 40-bit serial result:

8.5.2.5 TMU Calibration

The TMU calibration process is identical to a normal TMU time-stamp measurement. The process involves measuring a known interval and calculating the difference between the measured value and the actual value. The result is then stored into calibration registers inside the TMU. The TMU takes the stored calibration values and corrects the subsequent time-stamp measurements.

There are four calibration registers for each channel. These are identified as follows:

• A calibration register for positive sync edge and positive event edge
• A calibration register for positive sync edge and negative event edge
• A calibration register for negative sync edge and positive event edge
• A calibration register for negative sync edge and negative event edge

Calibration due to temperature changes following the initial system calibration may be required if temperature variations are significant.

8.5.2.6 Temperature Sensor

A temperature sensor has been located centrally in the THS788 device for monitoring the die temperature. There are two monitor outputs for this feature. An analog voltage proportional to the die temperature is presented at the TEMP pin. Also, an overtemperature alarm output is available at the OT_ALARM pin. The overtemperature alarm (OT_ALARM) is an open-drain output that is activated when the die temperature reaches 141°C.

The overtemperature alarm sets a register bit (OT_ALM) in the central register and may be accessed through the serial interface.

The overtemperature alarm initiates an automatic power down to prevent overheating of the device. The digital blocks remain functional when in automatic power down. Following a power down, the user is required to reset OT_ALM using the serial interface. A register bit (RST_OT_ALM) is used for this purpose.

The temperature-monitoring function and its associated overtemperarture alarm circuit may be disabled by the user, using a register bit (OT_EN). The default for the temperature-monitoring function is enabled.

OT_EN = 1: Temperature-monitoring function is enabled.
OT_EN = 0: Temperature-monitoring function is disabled.