SLLSFD6A May 2020 – March 2021 THVD8000
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
Driver | |||||||
|VOD| | Driver differential output voltage magnitude | RL = 60 Ω, –7 V ≤ Vtest ≤ 12 V, Measured at 2nd pulse | See Figure 7-1 | 1.5 | 3.5 | V | |
RL = 100 Ω, CL = 50 pF, Measured at 2nd pulse | See Figure 7-1 | 2 | 4 | ||||
RL = 54 Ω, CL = 50 pF, Measured at 2nd pulse | See Figure 7-1 | 1.5 | 3.5 | ||||
VOC | Steady state common-mode output voltage | RL = 60 Ω, CL = 50 pF | See Figure 7-2 | 1 | VCC / 2 | 3 | V |
ΔVOC | Change in differential driver common-mode output voltage | RL = 60 Ω, CL = 50 pF | See Figure 7-2 | -160 | 160 | mV | |
VOC(PP) | Peak-to-peak driver common-mode output voltage | RL = 60 Ω, CL = 50 pF, VCC = 3.3 V and VCC = 5V | See Figure 7-2 | 425 | mV | ||
IOS | Driver short-circuit output current | MODE = VCC, –7 V ≤ [VA or VB] ≤ 12 V | –250 | 250 | mA | ||
f0 | Minimum carrier frequency(1) | RF_SET = 77 kΩ | See Figure 7-3 | 125 | kHz | ||
Maximum carrier frequency(1) | RF_SET = 1.5 kΩ | 5 | MHz | ||||
DCDf0 | Carrier frequency duty cycle distortion | Measured over the full range of f0 | –2 | 2 | % | ||
Δf0 | Carrier frequency tolerance | Measured with a ±2% tolerant RF_SET | –25 | 25 | % | ||
ΔfSSC | Variation of the carrier frequency for spread spectrum clocking | Measured across the full carrier frequency range | ±5 | % | |||
fSSC | Spread spectrum clock rate | 30 | kHz | ||||
Receiver | |||||||
II | Bus input current in receive mode | MODE = GND, VCC = 0 V or 5.5 V | VI = 12 V | 75 | 125 | µA | |
VI = –7 V | –97 | –70 | |||||
VMAG_ZERO | OOK signal differential swing (magnitude) to detect a zero at the R output | MODE = GND, over full common mode range | 125 kHz | 225 | mV | ||
1 MHz | 150 | ||||||
5 MHz | 115 | ||||||
VMAG_ONE | OOK signal differential swing (magnitude) to detect a one at the R output | 125 kHz | 20 | mV | |||
1 MHz | 10 | ||||||
5 MHz | 10 | ||||||
VMAG_HYS | Receiver differential input voltage threshold hysteresis | 125 kHz | 40 | mV | |||
1 MHz | 20 | ||||||
5 MHz | 20 | ||||||
Logic / Control Pins | |||||||
IIN | Input current (D, MODE) | VO = 0 V or VCC | –5 | 5 | µA | ||
IIN | Input current (F_SET) | VO = VCC | 55 | µA | |||
VO | Output voltage (F_SET) | IO = 0 mA | 1.4 | V | |||
1.5 kΩ ≤ RPD ≤ 78 kΩ | 785 | mV | |||||
VOH | Receiver high-level output voltage | IOH = –4 mA | VCC – 0.4 | VCC – 0.2 | V | ||
VOL | Receiver low-level output voltage | IOL = 4 mA | 0.2 | 0.4 | V | ||
IOZ | Receiver high-impedance output current | VO = 0 V or VCC, MODE = 0 | –1 | 1 | µA | ||
Device | |||||||
ICC | Supply current (quiescent) | Transmit mode | D = VCC, MODE = VCC, resistor between F_SET and GND, no load | 3.1 | 5 | mA | |
Receive mode | D = VCC, MODE = GND, resistor between F_SET and GND, no load | 4 | 6 | ||||
TSD | Thermal shutdown temperature | 160 | 170 | 185 | ℃ | ||
THYS | Thermal shutdown hysteresis | 11 | 15 | ℃ |