SLLSEN8C September   2015  – June 2017 TL16C752D

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configurations and Function
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Functional Description
        1. 8.3.1.1  Trigger Levels
        2. 8.3.1.2  Hardware Flow Control
        3. 8.3.1.3  Auto-RTS
        4. 8.3.1.4  Auto-CTS
        5. 8.3.1.5  Software Flow Control
        6. 8.3.1.6  Software Flow Control Example
        7. 8.3.1.7  Reset
        8. 8.3.1.8  Interrupts
        9. 8.3.1.9  Interrupt Mode Operation
        10. 8.3.1.10 Polled Mode Operation
        11. 8.3.1.11 Break and Timeout Conditions
        12. 8.3.1.12 Programmable Baud Rate Generator
    4. 8.4 Device Functional Modes
      1. 8.4.1 DMA Signaling
        1. 8.4.1.1 Single DMA Transfers (DMA Mode0 or FIFO Disable)
        2. 8.4.1.2 Block DMA Transfers (DMA Mode 1)
      2. 8.4.2 Sleep Mode
    5. 8.5 Register Maps
      1. 8.5.1  Principals of Operation
      2. 8.5.2  Receiver Holding Register (RHR)
      3. 8.5.3  Transmit Holding Register (THR)
      4. 8.5.4  FIFO Control Register (FCR)
      5. 8.5.5  Line Control Register (LCR)
      6. 8.5.6  Line Status Register (LSR)
      7. 8.5.7  Modem Control Register (MCR)
      8. 8.5.8  Modem Status Register (MSR)
      9. 8.5.9  Interrupt Enable Register (IER)
      10. 8.5.10 Interrupt Identification Register (IIR)
      11. 8.5.11 Enhanced Feature Register (EFR)
      12. 8.5.12 Divisor Latches (DLL, DLH)
      13. 8.5.13 Transmission Control Register (TCR)
      14. 8.5.14 Trigger Level Register (TLR)
      15. 8.5.15 FIFO Ready Register
      16. 8.5.16 Alternate Function Register (AFR)
      17. 8.5.17 RS-485 Mode
      18. 8.5.18 IrDA Overview
      19. 8.5.19 IrDA Encoder Function
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 6 V
VI Input voltage –0.5 VCC + 0.5 V
VO Output voltage –0.5 VCC + 0.5 V
TA Operating free-air temperature –40 85 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC = 1.8 V ±10%
VCC Supply voltage 1.62 1.8 1.98 V
VI Input voltage –0.3 0.9 × VCC V
VIH High-level input voltage 1.4 V
VIL Low-level input voltage 0.4 V
VO Output voltage 0 VCC V
IOH High-level output current All outputs –0.5 mA
IOL Low-level output current All outputs 1 mA
Oscillator/clock speed 16 MHz
VCC = 2.5 V ±10%
VCC Supply voltage 2.25 2.5 2.75 V
VI Input voltage –0.3 0.9 × VCC V
VIH High-level input voltage 1.8 V
VIL Low-level input voltage 0.6 V
VO Output voltage 0 VCC V
IOH High-level output current All outputs –1 mA
IOL Low-level output current All outputs 2 mA
Oscillator/clock speed 24 MHz
VCC = 3.3 V ±10%
VCC Supply voltage 3 3.3 3.6 V
VI Input voltage –0.3 VCC V
VIH High-level input voltage 0.7 × VCC V
VIL Low-level input voltage 0.8 V
VO Output voltage 0 VCC V
IOH High-level output current All outputs –1.8 mA
IOL Low-level output current All outputs 3.2 mA
Oscillator or clock speed 48 MHz
VCC = 5 V ±10%
VCC Supply voltage 4.5 5 5.5 V
VI Input voltage –0.3 VCC V
VIH High-level input voltage Except XTAL1 2 V
XTAL1 0.7 × VCC
VIL Low-level input voltage Except XTAL1 0.8 V
XTAL1 0.3 × VCC
VO Output voltage 0 VCC V
IOH High-level output current All outputs –4 mA
IOL Low-level output current All outputs 4 mA
Oscillator or clock speed 48 MHz

7.4 Thermal Information

THERMAL METRIC(1) TL16C752D UNIT
PFB (TQFP)
48 PINS
RθJA Junction-to-ambient thermal resistance 61 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 17.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = 1.8 V
VOH High-level output voltage IOH = –0.5 mA 1.3 V
VOL Low-level output voltage IOL = 1 mA 0.5
II Input current VCC = 1.98 V,
VI = 0 to 1.98 V,		 VSS = 0,
All other terminals floating		 10 μA
IOZ High-impedance state
output current		 VCC = 1.98 V,
VO = 0 to 1.98 V,		 VSS = 0, ±20 μA
Chip selected in write mode or chip deselect
ICC Supply current VCC = 1.98 V, TA = 70°C, 4.5 mA
DSR, CTS, and RI at 2 V,
All other inputs at 0.4 V,
No load on outputs,		 XTAL1 at 16 MHz,
Baud rate = 1 Mb/s
CI(CLK) Clock input capacitance VCC = 0,
f = 1 MHz,
All other terminals grounded		 VSS = 0,
TA = 25°C,		 5 7 pF
CO(CLK) Clock output capacitance 5 7
CI Input capacitance 6 10
CO Output capacitance 10 15
VCC = 2.5 V
VOH High-level output voltage IOH = –1 mA 1.8 V
VOL Low-level output voltage IOL = 2 mA 0.5
II Input current VCC = 2.75 V,
VI = 0 to 2.75 V,		 VSS = 0,
All other terminals floating		 10 μA
IOZ High-impedance state output current VCC = 2.75 V,
VO = 0 to 2.75 V,		 VSS = 0, ±20 μA
Chip selected in write mode or chip deselect
ICC Supply current VCC = 2.75 V, TA = 70°C, 9 mA
DCD, CTS, and RI at 2 V,
All other inputs at 0.6 V,
No load on outputs,		 XTAL1 at 24 MHz,
Baud rate = 1.5 Mb/s
CI(CLK) Clock input capacitance VCC = 0,
f = 1 MHz,
All other terminals grounded		 VSS = 0,
TA = 25°C,		 5 7 pF
CO(CLK) Clock output capacitance 5 7
CI Input capacitance 6 10
CO Output capacitance 10 15
VCC = 3.3 V
VOH High-level output voltage IOH = –1.8 mA 2.4 V
VOL Low-level output voltage IOL = 3.2 mA 0.5
II Input current VCC = 3.6 V,
VI = 0 to 3.6 V,		 VSS = 0,
All other terminals floating		 10 μA
IOZ High-impedance state
output current		 VCC = 3.6 V,
VO = 0 to 3.6 V,		 VSS = 0, ±20 μA
Chip selected in write mode or chip deselect
ICC Supply current VCC = 3.6 V, TA = 70°C, 16 mA
DSR, CTS, and RI at 2 V,
All other inputs at 0.8 V,
No load on outputs,		 XTAL1 at 32 MHz,
Baud rate = 2 Mb/s
CI(CLK) Clock input capacitance VCC = 0,
f = 1 MHz,
All other terminals grounded		 VSS = 0,
TA = 25°C,		 5 7 pF
CO(CLK) Clock output capacitance 5 7
CI Input capacitance 6 10
CO Output capacitance 10 15
VCC = 5 V
VOH High-level output voltage IOH = –4 mA 4 V
VOL Low-level output voltage IOL = 4 mA 0.5
II Input current VCC = 5.5 V,
VI = 0 to 5.5 V,		 VSS = 0,
All other terminals floating		 10 μA
IOZ High-impedance state
output current		 VCC = 5.5 V,
VO = 0 to 5.5 V,		 VSS = 0, ±20 μA
Chip selected in write mode or chip deselect
ICC Supply current VCC = 5.5 V, TA = 70°C, 40 mA
DSR, CTS, and RI at 2 V,
All other inputs at 0.8 V,
No load on outputs,		 XTAL1 at 48 MHz,
Baud rate = 3 Mb/s
CI(CLK) Clock input capacitance VCC = 0,
f = 1 MHz,
All other terminals grounded		 VSS = 0,
TA = 25°C,		 5 7 pF
CO(CLK) Clock output capacitance 5 7
CI Input capacitance 6 10
CO Output capacitance 10 15

7.6 Timing Requirements

TA = 0°C to 70°C, VCC = 1.8 V to 5 V ±10% (unless otherwise noted)
LIMITS UNIT
1.8 V 2.5 V 3.3 V 5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tRESET Reset pulse width 200 200 200 200 ns
CP CP clock period 63 42 20 20 ns
t3w Oscillator or clock speed 16 24 48 48 MHz
t6s Address setup time 20 15 10 5 ns
t6h Address hold time See Figure 1 and Figure 2 15 10 7 5 ns
t7w IOR strobe width See Figure 1 and Figure 2 85 70 50 40 ns
t9d Read cycle delay See Figure 2 85 70 60 50 ns
t12d Delay from IOR to data See Figure 2 65 50 35 25 ns
t12h Data disable time 35 25 20 15 ns
t13w IOW strobe width See Figure 1 85 70 50 40 ns
t15d Write cycle delay See Figure 1 85 70 60 50 ns
t16s Data setup time See Figure 1 40 30 20 15 ns
t16h Data hold time See Figure 1 35 25 15 10 ns
t17d Delay from IOW to output 50-pF load, see Figure 3 60 40 30 20 ns
t18d Delay to set interrupt from MODEM input 50-pF load, see Figure 3 70 55 45 35 ns
t19d Delay to reset interrupt from IOR 50-pF load 80 55 40 30 ns
t20d Delay from stop to set interrupt See Figure 4 1 1 1 1 baudrate
t21d Delay from IOR to reset interrupt 50-pF load, see Figure 4 55 45 35 25 ns
t22d Delay from stop to interrupt See Figure 7 1 1 1 1 baudrate
t23d Delay from initial IOW reset to transmit start See Figure 7 8 24 8 24 8 24 8 24 baudrate
t24d Delay from IOW to reset interrupt See Figure 7 75 45 35 25 ns
t25d Delay from stop to set RXRDY See Figure 5 and Figure 6 1 1 1 1 baudrate
t26d Delay from IOR to reset RXRDY See Figure 5 and Figure 6 1 1 1 1 μs
t27d Delay from IOW to set TXRDY See Figure 8 and Figure 9 70 60 50 40 ns
t28d Delay from start to reset TXRDY See Figure 8 and Figure 9 16 16 16 16 baudrate
TL16C752D genwritetim_lls646.gif Figure 1. General Write Timing
TL16C752D genreadtim_lls646.gif Figure 2. General Read Timing
TL16C752D modeminouttim_lls646.gif Figure 3. Modem or Output Timing
TL16C752D receivetim_lls646.gif Figure 4. Receive Timing
TL16C752D recrdytim_nofifo_ll646.gif Figure 5. Receive Ready Timing in Non-FIFO Mode
TL16C752D receivetim_fifo_lls646.gif Figure 6. Receive Timing in FIFO Mode
TL16C752D transmittim_lls646.gif Figure 7. Transmit Timing
TL16C752D transmitrdy_nofifo_lls646.gif Figure 8. Transmit Ready Timing in Non-FIFO Mode
TL16C752D transmitrdy_fifo_lls646.gif Figure 9. Transmit Timing in FIFO Mode

7.7 Typical Characteristics

all channels active, TA = 25°C, unless otherwise noted
TL16C752D D001_SLLS646.gif
Figure 10. Supply Current vs Frequency (VCC = 1.62, 1.8, and 1.98 V)
TL16C752D D003_SLLS646.gif
Figure 12. Supply Current vs Frequency (VCC = 3, 3.3, and 3.5 V)
TL16C752D D002_SLLS646.gif
Figure 11. Supply Current vs Frequency (VCC = 2.25, 2.5, and 2.75 V)
TL16C752D g_icc_freq_50_lls646.gif
Figure 13. Supply Current vs Frequency (VCC = 5 V)