SLVS934C June   2009  – February 2021 TLC59025

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics for 3-V Input Voltage
    6. 6.6  Electrical Characteristics for 5.5-V Input Voltage
    7. 6.7  Power Dissipation Ratings
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics for 3-V Input Voltage
    10. 6.10 Switching Characteristics for 5.5-V Input Voltage
    11. 6.11 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Constant Current
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Turning on the LEDs
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Adjusting Output Current
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Support Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Switching Characteristics for 3-V Input Voltage

VDD = 3 V, TA = –40°C to 125°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tPLH1Low-to-high propagation delay time, CLK to OUTnVIH = VDD, VIL = GND,
Rext = 720 Ω, VL = 4 V,
RL = 88 Ω, CL = 10 pF
304560ns
tPLH2Low-to-high propagation delay time, LE to OUTn304560ns
tPLH3Low-to-high propagation delay time, OE to OUTn304560ns
tPLH4Low-to-high propagation delay time, CLK to SDO3040ns
tPHL1High-to-low propagation delay time, CLK to OUTn4065100ns
tPHL2High-to-low propagation delay time, LE to OUTn4065100ns
tPHL3High-to-low propagation delay time, OE to OUTn4065100ns
tPHL4High-to-low propagation delay time, CLK to SDO3040ns
tw(CLK)Pulse duration, CLK15ns
tw(L)Pulse duration LE15ns
tw(OE)Pulse duration, OE300ns
th(D)Hold time, SDI2ns
tsu(D)Setup time, SDI3ns
th(L)Hold time, LE5ns
tsu(L)Setup time, LE5ns
trRise time, CLK (1)500ns
tfFall time, CLK (1)500ns
torRise time, outputs (off)355070ns
tofRise time, outputs (on)1550120ns
fCLKClock frequencyCascade operation30MHz
If the devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices.