9.3.1 Open-Circuit Detection Principle

The LED Open-Circuit Detection compares the effective current level I_out with the open load detection threshold current I_OUT,Th. If I_OUT is below the I_OUT,Th threshold, the TLC591x-Q1 detects an open-load condition. This error status can be read as an error status code in the Special mode. For open-circuit error detection, a channel must be on.

9.3.2 Short-Circuit Detection Principle (TLC5917-Q1 Only)

The LED short-circuit detection compares the effective voltage level (V_OUT) with the shorted-load detection threshold voltages V_OUT,TTh and V_OUT,RTh. If V_OUT is above the V_OUT,TTh threshold, the TLC5917-Q1 detects an shorted-load condition. If V_OUT is below the V_OUT,RTh threshold, no error is detected and the error bit is reset. This error status can be read as an error status code in the Special mode. For short-circuit error detection, a channel must be on.

Figure 9. Short-Circuit Detection Principle

9.3.3 Overtemperature Detection and Shutdown

TLC591x-Q1 is equipped with a global overtemperature sensor and eight individual, channel-specific, overtemperature sensors.

• When the global sensor reaches the trip temperature, all output channels are shutdown, and the error status is stored in the internal Error Status register of every channel. After shutdown, the channels automatically restart after cooling down, if the control signal (output latch) remains on. The stored error status is not reset after cooling down and can be read out as the error status code in the Special mode.
• When one of the channel-specific sensors reaches trip temperature, only the affected output channel is shut down, and the error status is stored only in the internal Error Status register of the affected channel. After shutdown, the channel automatically restarts after cooling down, if the control signal (output latch) remains on. The stored error status is not reset after cooling down and can be read out as error status code in the Special mode.

For channel-specific overtemperature error detection, a channel must be on.

The error status code is reset when TLC591x-Q1 returns to Normal mode.

Table 4. Truth Table in Normal Mode

9.4.1 Operation Mode Switching

In order to switch between its two modes, TLC591x-Q1 monitors the signal OE(ED2). When an one-clock-wide pulse of OE(ED2) appears, TLC591x-Q1 enters the two-clock-period transition phase, the Mode Switching phase. After power on, the default operation mode is the Normal Mode (see Figure 15).

Figure 15. Mode Switching

As shown in Figure 15, once a one-clock-wide short pulse (101) of OE(ED2) appears, TTLC591x-Q1 enters the Mode Switching phase. At the fourth rising edge of CLK, if LE(ED1) is sampled as voltage high, TLC591x-Q1 switches to Special mode; otherwise, it switches to Normal mode. The signal LE(ED1) between the third and the fifth rising edges of CLK cannot latch any data. Its level is used only to determine into which mode to switch. However, the short pulse of OE(ED2) can still enable the output ports. During mode switching, the serial data can still be transferred through SDI and shifted out from SDO.

9.5.1 Reading Error Status Code in Special Mode

When OE(ED2) is pulled low while in Special mode, error detection and load error status codes are loaded into the Shift register, in addition to enabling output ports to sink current. Figure 16 shows the timing sequence for error detection. The 0 and 1 signal levels are sampled at the rising edge of each CLK. At least three zeros must be sampled at the voltage low signal OE(ED2). Immediately after the second zero is sampled, the data input source of the Shift register changes to the 8-bit parallel Error Status Code register, instead of from the serial data on SDI. Normally, the error status codes are generated at least 2 μs after the falling edge of OE(ED2). The occurrence of the third or later zero saves the detected error status codes into the Shift register. Therefore, when OE(ED2) is low, the serial data cannot be shifted into TLC591x-Q1 via SDI. When OE(ED2) is pulled high, the data input source of the Shift register is changed back to SDI. At the same time, the output ports are disabled and the error detection is completed. Then, the error status codes saved in the Shift register can be shifted out via SDO bit by bit along with CLK, as well as the new serial data can be shifted into TLC591x-Q1 via SDI.

While in Special mode, the TLC591x-Q1 cannot simultaneously transfer serial data and detect LED load error status.

Figure 16. Reading Error Status Code

9.5.2 Writing Configuration Code in Special Mode

When in Special mode, the active high signal LE(ED1) latches the serial data in the Shift register to the Configuration Latch, instead of the Output Latch. The latched serial data is used as the Configuration Code.

The code is stored until power off or the Configuration Latch is rewritten. As shown in Figure 17, the timing for writing the Configuration Code is the same as the timing in the Normal Mode to latching output channel data. Both the Configuration Code and Error Status Code are transferred in the common 8-bit Shift register. Users must pay attention to the sequence of error detection and current adjustment to avoid the Configuration Code being overwritten by Error Status Code.

Figure 17. Writing Configuration Code

9.5.3 8-Bit Configuration Code and Current Gain

Bit definition of the Configuration Code in the Configuration Latch is shown in Table 5.

Bit 7 is first sent into TLC591x-Q1 via SDI. Bits 1 to 7 {HC, CC[0:5]} determine the voltage gain (VG) that affects the voltage at R-EXT and indirectly affects the reference current, I_ref, flowing through the external resistor at R-EXT. Bit 0 is the Current Multiplier (CM) that determines the ratio I_OUT,target/I_ref. Each combination of VG and CM gives a specific Current Gain (CG).

• VG: the relationship between {HC,CC[0:5]} and the voltage gain is calculated as shown below:

VG = (1 + HC) × (1 + D/64) / 4

D = CC0 × 2⁵ + CC1 × 2⁴ + CC2 × 2³ + CC3 × 2² + CC4 × 2¹ + CC5 × 2⁰

Where HC is 1 or 0, and D is the binary value of CC[0:5]. So, the VG could be regarded as a floating-point number with 1-bit exponent HC and 6-bit mantissa CC[0:5]. {HC,CC[0:5]} divides the programmable voltage gain VG into 128 steps and two sub-bands:

Low-voltage subband (HC = 0): VG = 1/4 ~ 127/256, linearly divided into 64 steps

High-voltage subband (HC = 1): VG = 1/2 ~ 127/128, linearly divided into 64 steps

• CM: In addition to determining the ratio I_OUT,target/I_ref, CM limits the output current range.

High Current Multiplier (CM = 1): I_OUT,target/I_ref = 15, suitable for output current range I_OUT = 10 mA to 120 mA.

Low Current Multiplier (CM = 0): I_OUT,target/I_ref = 5, suitable for output current range I_OUT = 5 mA to 40 mA

• CG: The total Current Gain is defined as the following.

V_R-EXT = 1.26 V × VG

I_ref = V_R-EXT/R_ext, if the external resistor, R_ext, is connected to ground.

I_OUT,target = I_ref × 15 × 3^{CM – 1} = 1.26 V/R_ext × VG × 15 × 3^CM – 1 = (1.26 V/R_ext × 15) × CG

CG = VG × 3^CM – 1

Therefore, CG = 1/12 to 127/128, and it is divided into 256 steps.

Examples

• Configuration Code {CM, HC, CC[0:5]} = {1,1,111111}

VG = 127/128 = 0.992 and CG = VG × 3⁰ = VG = 0.992

• Configuration Code = {1,1,000000}

VG = (1 + 1) × (1 + 0/64)/4 = 1/2 = 0.5, and CG = 0.5

• Configuration Code = {0,0,000000}

VG = (1 + 0) × (1 + 0/64)/4 = 1/4, and CG = (1/4) × 3^–1 = 1/12

After power on, the default value of the Configuration Code {CM, HC, CC[0:5]} is {1,1,111111}. Therefore, VG = CG = 0.992. The relationship between the Configuration Code and the Current Gain is shown in Figure 18.

Figure 18. Current Gain vs Configuration Code