SLVSEB3A June   2018  – January 2019 TLC6946 , TLC6948

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic of TLC6948 With 48-Multiplexing
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Pin Equivalent Input and Output Schematic Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Built-In 16Kb Display Memory (SRAM)
      2. 9.3.2  GCLK Dual-Edge Operation
      3. 9.3.3  Programmable Constant-Sink Channel Current
        1. 9.3.3.1 Global Brightness Control (BC)
        2. 9.3.3.2 Select RIREF for a Given BC
      4. 9.3.4  Grayscale (GS) Function (PWM Control)
      5. 9.3.5  Serial Data Interface
      6. 9.3.6  LED-Open Detection (LOD)
      7. 9.3.7  Caterpillar Removal
      8. 9.3.8  Precharge FET
      9. 9.3.9  Thermal Shutdown
      10. 9.3.10 IREF Resistor Short Protection (ISP)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Operating Mode
      2. 9.4.2 Power-Save Mode (PSM)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 Power Supply Voltage
        2. 10.2.2.2 Channel Current and Brightness Control
        3. 10.2.2.3 SCLK and GCLK Frequency
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DBQ Package
24-Pin SSOP
Top View
RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
DBQ RGE
GCLK 21 20 I Grayscale (GS) pulse-width modulation (PWM) reference-clock-signal input pin. In the default operating mode, each GCLK rising edge increments the GS counter for PWM control. GCLK supports dual-edge operation.
GND 1 10 — Power-ground reference
IREF 23 21 I Pin for setting the maximum constant-current value. Connecting an external resistor between IREF and GND sets the maximum current for each constant-current output channel. When this pin is connected directly to GND, all outputs are forced off. The external resistor should be placed close to the device.
LAT 4 1 I Data latch pin. The falling edge of LAT latches the data from the common shift register into the GS data memory or the function control register.
OUT0 5 2 O Constant-current output. Each output can be tied together with others to increase the constant current. A different voltage can be applied to each output.
OUT1 6 3 O
OUT2 7 4 O
OUT3 8 5 O
OUT4 9 6 O
OUT5 10 7 O
OUT6 11 8 O
OUT7 12 9 O
OUT8 13 11 O
OUT9 14 12 O
OUT10 15 13 O
OUT11 16 14 O
OUT12 17 15 O
OUT13 18 16 O
OUT14 19 17 O
OUT15 20 18 O
SCLK 3 24 I Clock-signal input pin. Serial data present on SIN are shifted to the LSB of the internal 16-bit common shift register on the SCLK rising edge. All data in the shift register are shifted toward the MSB of the internal 16-bit common shift register on each SCLK rising edge.
SIN 2 23 I Serial-data input pin of the internal 16-bit common shift register. When SIN is high, the LSB of the internal 16-bit common shift register is set to 1 on the SCLK input rising edge. When SIN is low, the LSB of the internal 16-bit common shift register is set to 0 on the SCLK input rising edge.
SOUT 22 19 O Serial data output pin of the internal 16-bit common shift register. The MSB of the internal 16-bit common shift register appears on SOUT.
VCC 24 22 I Power supply pin
Thermal pad — — — Internally connected to GND in the RGE package only. The thermal pad and the GND pin must be connected together on the board.