SBVS283F August   2016  – October 2020 TLV733P-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout (UVLO)
      2. 7.3.2 Shutdown and Output Enable
      3. 7.3.3 Internal Foldback Current Limit
      4. 7.3.4 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
      2. 8.1.2 Dropout Voltage
    2. 8.2 Typical Applications
      1. 8.2.1 DC-DC Converter Post Regulation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Design Considerations
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Capacitor-Free Operation from a Battery Input Supply
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Design Considerations
        3. 8.2.2.3 Application Curve
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Examples
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Evaluation Module
      2. 10.1.2 Device Nomenclature
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TLV733P-Q1 family of low dropout (LDO) linear regulators are ultra-small, low quiescent current LDOs that can source 300 mA with good line and load transient performance. These devices provide a typical accuracy of 1%.

The TLV733P-Q1 family is designed with a modern capacitor-free architecture to ensure stability without an input or output capacitor. The removal of the output capacitor allows for a very small solution size, and can eliminate inrush current at startup. Furthermore, the TLV733P-Q1 family is also stable with ceramic output capacitors if an output capacitor is necessary. The TLV733P-Q1 family also provides foldback current control during device power-up and enabling if an output capacitor is used. This functionality is especially important in battery-operated devices.

The TLV733P-Q1 family provides an active pulldown circuit to quickly discharge output loads when disabled.

The TLV733P-Q1 family is available in the 6-pin DRV (WSON) and 5-pin DBV (SOT-23) packages.

Device Information(1)
PART NUMBERPACKAGEBODY SIZE (NOM)
TLV733P-Q1WSON (6)2.00 mm × 2.00 mm
SOT-23 (5)2.90 mm × 1.60 mm
(1) For all available packages, see the package option addendum at the end of the data sheet.

 

GUID-9DB6C7F7-698D-4F8F-B0A4-0720B559BFFB-low.gifTypical Application Circuit
GUID-725979AA-E1D6-45B9-B620-AB373C791E8A-low.gifDropout Voltage vs Output Current