SBOS942J August   2018  – February 2024 TLV9051 , TLV9052 , TLV9054

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V
    8. 6.8 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Rail-to-Rail Input
      3. 7.3.3 Rail-to-Rail Output
      4. 7.3.4 EMI Rejection
      5. 7.3.5 Overload Recovery
      6. 7.3.6 Packages With an Exposed Thermal Pad
      7. 7.3.7 Electrical Overstress
      8. 7.3.8 Input Protection
      9. 7.3.9 Shutdown Function
    4. 7.4 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Low-Side Current Sense Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics

at TA = 25°C, VS = 5.5V, RL = 10kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)

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VS = 5.5V
Figure 6-1 Offset Voltage Production Distribution
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Figure 6-3 Offset Voltage vs Temperature
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Figure 6-5 Offset Voltage vs Power Supply
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Figure 6-7 Input Bias Current and Offset Current vs Common-Mode Voltage
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Figure 6-9 Input Voltage Noise Spectral Density vs Frequency
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Figure 6-11 CMRR vs Temperature
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VS = 5.5V, TA = –40°C to 125°C
Figure 6-2 Offset Voltage Drift Distribution
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Figure 6-4 Offset Voltage vs Common-Mode Voltage
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Figure 6-6 Input Bias Current vs Temperature
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Figure 6-8 0.1-Hz to 10-Hz Input Voltage Noise
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Figure 6-10 CMRR and PSRR vs Frequency (Referred to Input)
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VS = 1.8V to 5.5V
Figure 6-12 PSRR vs Temperature
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Figure 6-13 Open Loop Voltage Gain and Phase vs Frequency
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Figure 6-15 Open Loop Voltage Gain vs Output Voltage
GUID-4AEA0C63-2422-4DBF-A967-555CB8C1F3B8-low.gifFigure 6-17 Phase Margin vs Capacitive Load
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G = +1V/V
VOUT step = 100mVp-p
Figure 6-19 Small-Signal Overshoot vs Load Capacitance
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Figure 6-21 Slew Rate vs Capacitive Load
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G = +1V/V
VOUT step = 10mVp-p
Figure 6-23 Small-Signal Step Response
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G = +1V/V
VOUT step = 4Vp-p
Figure 6-25 Large-Signal Step Response
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CL = 100pFG = +1V/V
Figure 6-27 Positive Large-Signal Settling Time
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VOUT = 0.5VRMSG = +1VCM = 2.5V
BW = 80kHz
Figure 6-29 THD + N vs Frequency
GUID-C6822799-CCF5-4B7C-9ED0-EDCDBD93D43A-low.gif
Figure 6-31 Output Voltage Swing vs Output Current
GUID-67499766-D9B0-48FE-A885-C8E3813C7AB6-low.gifFigure 6-33 Short-Circuit Current vs Temperature
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Figure 6-35 Quiescent Current vs Temperature
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PRF = –10dBm
Figure 6-37 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency
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Figure 6-14 Open Loop Voltage Gain vs Temperature
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Figure 6-16 Closed Loop Voltage Gain vs Frequency
GUID-79313143-A8B9-4BB0-A004-70186B9F86E5-low.gifFigure 6-18 No Phase Reversal
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G = –1V/V
VOUT step = 100mVp-p
Figure 6-20 Small-Signal Overshoot vs Load Capacitance
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G = –10V/V
Figure 6-22 Overload Recovery
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G = –1V/V
VOUT step = 10mVp-p
Figure 6-24 Small-Signal Step Response
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G = –1V/V
VOUT step = 4Vp-p
Figure 6-26 Large-Signal Step Response
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CL = 100pFG = +1V/V
Figure 6-28 Negative Large-Signal Settling Time
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f = 1kHzG = +1VCM = 2.5V
BW = 80kHz
Figure 6-30 THD + N vs Amplitude
GUID-94AFE59D-0FBA-43BA-91A9-07EA9759516E-low.gifFigure 6-32 Maximum Output Voltage vs Frequency and Supply Voltage
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Figure 6-34 Quiescent Current vs Supply Voltage
GUID-ACC265F0-430D-4B99-BB7E-44826B70382A-low.gifFigure 6-36 Open-Loop Output Impedance vs Frequency
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PRF = –10dBm
Figure 6-38 Channel Separation vs Frequency