SCDS412B June   2019  – January 2024 TMUX1133 , TMUX1134

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics (VDD = 5V ±10 %)
    6. 6.6  Electrical Characteristics (VDD = 3.3V ±10 %)
    7. 6.7  Electrical Characteristics (VDD = 2.5V ±10 %), (VSS = –2.5V ±10 %)
    8. 6.8  Electrical Characteristics (VDD = 1.8V ±10 %)
    9. 6.9  Electrical Characteristics (VDD = 1.2V ±10 %)
    10. 6.10 Typical Characteristics
  8. Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Transition Time
    5. 7.5  Break-Before-Make
    6. 7.6  tON(EN) and tOFF(EN)
    7. 7.7  Charge Injection
    8. 7.8  Off Isolation
    9. 7.9  Crosstalk
    10. 7.10 Bandwidth
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail to Rail Operation
      3. 8.3.3 1.8V Logic Compatible Inputs
      4. 8.3.4 Fail-Safe Logic
      5. 8.3.5 Ultra-low Leakage Current
      6. 8.3.6 Ultra-Low Charge Injection
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Ultra-Low Charge Injection

The TMUX113x devices have a transmission gate topology, as shown in Figure 8-2. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

The TMUX113x devices have special charge-injection cancellation circuitry that reduces the source-to-drain charge injection to -1pC at VS = 1V as shown in Figure 8-3.

GUID-0040BE35-F6FB-448D-80DC-8147652BDD3F-low.gifFigure 8-2 Transmission Gate Topology
GUID-977B8F5B-5A08-4583-8BE9-CD4305FACFAD-low.gifFigure 8-3 Charge Injection vs Source Voltage