9.3.1 Operation With DACs and CODECs

In using Class-D amplifiers with CODECs and DACs, sometimes there is an increase in the output noise floor from the audio amplifier. This occurs when mixing of the output frequencies of the CODEC/DAC mix with the switching frequencies of the audio amplifier input stage. The noise increase can be solved by placing a lowpass filter between the CODEC/DAC and audio amplifier. This filters off the high frequencies that cause the problem and allow proper performance (see Functional Block Diagram).

If driving the TPA2016D2 input with 4th-order or higher ΔΣ DACs or CODECs, add an RC lowpass filter at each of the audio inputs (IN+ and IN–) of the TPA2016D2 to ensure best performance. The recommended resistor value is 100 Ω and the capacitor value of 47 nF.

9.3.2 Filter-Free Operation and Ferrite Bead Filters

A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter and the frequency sensitive circuit is greater than 1 MHz. This filter functions well for circuits that just have to pass FCC and CE because FCC and CE only test radiated emissions greater than 30 MHz. When choosing a ferrite bead, choose one with high impedance at high frequencies, and low impedance at low frequencies. In addition, select a ferrite bead with adequate current rating to prevent distortion of the output signal.

Use an LC output filter if there are low-frequency (< 1 MHz), EMI-sensitive circuits or there are long leads from amplifier to speaker. Figure 26 shows typical ferrite bead and LC output filters.

Figure 26. Typical Ferrite Bead Filter (Chip Bead Example: TDK: MPZ1608S221A)

9.3.3 Short-Circuit Protection

TPA2016D2 goes to low duty cycle mode when a short circuit event happens. In order to go to normal duty cycle mode again, it is necessary to reset the device, the shutdown mode can be set through the SDZ pin or software shutdown with the SWS bit. FAULT bit (register 1, bit 3) set to high when short-circuit event happens. It requires a write to clear.

This feature can protect the device without affecting the device’s long-term reliability.

9.3.4 Automatic Gain Control

The Automatic Gain Control (AGC) feature provides continuous automatic gain adjustment to the amplifier through an internal PGA. This feature enhances the perceived audio loudness and at the same time prevents speaker damage from occurring (Limiter function).

The AGC function attempts to maintain the audio signal gain as selected by the user through the Fixed Gain, Limiter Level, and Compression Ratio variables. Other advanced features included are Maximum Gain and Noise Gate Threshold. Table 1 describes the function of each variable in the AGC function.

The AGC works by detecting the audio input envelope. The gain changes depending on the amplitude, the limiter level, the compression ratio, and the attack and release time. The gain changes constantly as the audio signal increases and/or decreases to create the compression effect. The gain step size for the AGC is 0.5 dB. If the audio signal has near-constant amplitude, the gain does not change. Figure 27 shows how the AGC works.

A. Gain decreases with no delay; attack time is reset. Release time and hold time are reset.

B. Signal amplitude above limiter level, but gain cannot change because attack time is not over.

C. Attack time ends; gain is allowed to decrease from this point forward by one step. Gain decreases because the amplitude remains above limiter threshold. All times are reset

D. Gain increases after release time finishes and signal amplitude remains below desired level. All times are reset after the gain increase.

E. Gain increases after release time is finished again because signal amplitude remains below desired level. All times are reset after the gain increase.

Figure 27. Input and Output Audio Signal vs Time

Because the number of gain steps is limited the compression region is limited as well. Figure 28 shows how the gain changes versus the input signal amplitude in the compression region.

Figure 28. Input Signal Voltage vs Gain

Thus the AGC performs a mapping of the input signal versus the output signal amplitude. This mapping can be modified according to the variables from Table 1.

The following graphs and explanations show the effect of each variable to the AGC independently; consider them when choosing values.

9.3.4.1 Fixed Gain

The fixed gain determines the initial gain of the AGC. Set the gain using the following variables:

• Set the fixed gain to be equal to the gain when the AGC is disabled.
• Set the fixed gain to maximize SNR.
• Set the fixed gain such that it does not overdrive the speaker.

Figure 29 shows how the fixed gain influences the input signal amplitude versus the output signal amplitude state diagram. The dotted 1:1 line is displayed for reference. The 1:1 line means that for a 1-dB increase in the input signal, the output increases by 1 dB.

Figure 29. Output Signal vs Input Signal State Diagram Showing Different Fixed Gain Configurations

If the Compression function is enabled, the Fixed Gain is adjustable from –28 dB to 30 dB. If the Compression function is disabled, the Fixed gain is adjustable from 0 dB to 30 dB.

9.3.4.2 Limiter Level

The Limiter level sets the maximum amplitude allowed at the output of the amplifier. The limiter should be set with the following constraints in mind:

• Below or at the maximum power rating of the speaker
• Below the minimum supply voltage in order to avoid clipping

Figure 30 shows how the limiter level influences the input signal amplitude versus the output signal amplitude state diagram.

Figure 30. Output Signal vs Input Signal State Diagram Showing Different Limiter Level Configurations

The limiter level and the fixed gain influence each other. If the fixed gain is set high, the AGC has a large limiter range. The fixed gain is set low, the AGC has a short limiter range. Figure 31 illustrates the two examples:

Figure 31. Output Signal vs Input Signal State Diagram Showing Same Limiter Level Configurations With Different Fixed Gain Configurations

9.3.4.3 Compression Ratio

The compression ratio sets the relation between input and output signal outside the limiter level region. The compression ratio compresses the dynamic range of the audio. For example if the audio source has a dynamic range of 60 dB and compression ratio of 2:1 is selected, then the output has a dynamic range of 30 dB. Most small form factor speakers have small dynamic range. Compression ratio allows audio with large dynamic range to fit into a speaker with small dynamic range.

The compression ratio also increases the loudness of the audio without increasing the peak voltage. The higher the compression ratio, the louder the perceived audio.

For example:

• A compression ratio of 4:1 is selected (meaning that a 4-dB change in the input signal results in a 1-dB signal change at the output)
• A fixed gain of 0 dB is selected and the maximum audio level is at 0 dBV.

When the input signal decreases to –32 dBV, the amplifier increases the gain to 24 dB in order to achieve an output of –8 dBV. The output signal amplitude equation is:

Equation 1.

In this example:

Equation 2.

The gain change equation is:

Equation 3.

Equation 4.

Consider the following when setting the compression ratio:

• Dynamic range of the speaker
• Fixed gain level
• Limiter Level
• Audio Loudness vs Output Dynamic Range.

Figure 32 shows different settings for dynamic range and different fixed gain selected but no limiter level.

Figure 32. Output Signal vs Input Signal State Diagram Showing Different Compression Ratio Configurations With Different Fixed Gain Configurations

The rotation point is always at Vin = 10 dBV. The rotation point is not located at the intersection of the limiter region and the compression region. By changing the fixed gain the rotation point will move in the y-axis direction only, as shown in the previous graph.

9.3.4.4 Interaction Between Compression Ratio and Limiter Range

The compression ratio can be limited by the limiter range. Note that the limiter range is selected by the limiter level and the fixed gain.

For a setting with large limiter range, the amount of gain steps in the AGC remaining to perform compression are limited. Figure 33 shows two examples, where the fixed gain was changed.

1. Small limiter range yielding a large compression region (small fixed gain).
2. Large limiter range yielding a small compression region (large fixed gain).

Figure 33. Output Signal vs Input Signal State Diagram Showing the Effects of the Limiter Range to the Compression Region

9.3.4.5 Noise Gate Threshold

The noise gate threshold prevents the AGC from changing the gain when there is no audio at the input of the amplifier. The noise gate threshold stops gain changes until the input signal is above the noise gate threshold. Select the noise gate threshold to be above the noise but below the minimum audio at the input of the amplifier signal. A filter is needed between delta-sigma CODEC/DAC and TPA2016D2 for effectiveness of the noise gate function. The filter eliminates the out-of-band noise from delta-sigma modulation and keeps the CODEC/DAC output noise lower than the noise gate threshold.

Figure 34. Time Diagram Showing the Relationship Between Input Signal Amplitude, Noise Gate Threshold and Gain Versus Time

9.3.4.6 Maximum Gain

This variable limits the number of gain steps in the AGC. This feature is useful in order to accomplish a more advanced output signal vs input signal transfer characteristic.

For example, to prevent the gain from going above a certain value, reduce the maximum gain.

However, this variable will affect the limiter range and the compression region. If the maximum gain is decreased, the limiter range and compression region is reduced. Figure 35 illustrates the effects.

Figure 35. Output Signal vs Input Signal State Diagram Showing Different Maximum Gains

A particular application requiring maximum gain of 22 dB, for example. Thus, set the maximum gain at 22 dB. The amplifier gain will never have a gain higher than 22 dB; however, this will reduce the limiter range.

9.3.4.7 Attack, Release, and Hold Time

• The attack time is the minimum time between gain decreases.
• The release time is the minimum time between gain increases.
• The hold time is the minimum time between a gain decrease (attack) and a gain increase (release). The hold time can be deactivated. Hold time is only valid if greater than release time.

Successive gain decreases are never faster than the attack time. Successive gain increases are never faster than the release time.

All time variables (attack, release, and hold) start counting after each gain change performed by the AGC. The AGC is allowed to decrease the gain (attack) only after the attack time finishes. The AGC is allowed to increase the gain (release) only after the release time finishes counting. However, if the preceding gain change was an attack (gain increase) and the hold time is enabled and longer than the release time, then the gain is only increased after the hold time.

The hold time is only enabled after a gain decrease (attack). The hold time replaces the release time after a gain decrease (attack). If the gain needs to be increased further, then the release time is used. The release time is used instead of the hold time if the hold time is disabled.

The attack time should be at least 100 times shorter than the release and hold time. The hold time should be the same or greater than the release time. It is important to select reasonable values for those variables in order to prevent the gain from changing too often or too slow.

Figure 36 illustrates the relationship between the three time variables.

Figure 36. Time Diagram Showing the Relation Between the Attack, Release, and Hold Time vs Input Signal Amplitude and Gain

Figure 37 shows a state diagram of the input signal amplitude vs the output signal amplitude and a summary of how the variables from Table 1 affect them.

Figure 37. Output Signal vs Input Signal State Diagram

9.4.1 TPA2016D2 AGC Operation

The TPA2016D2 is controlled by the I²C interface. The correct start-up sequence is:

1. Apply the supply voltage to the AV_DD and PV_DD (L, R) pins.
2. Apply a voltage above V_IH to the SDZ pin. The TPA2016D2 powers up the I²C interface and the control logic. By default, the device is in active mode (SWS = 0). After a few milliseconds the amplifier will enable the class-D output stage and become fully operational.
3. The amplifier starts at a gain of 0 dB and the AGC starts ramping the gain after the input signal exceeds the noise gate threshold.

The default conditions of TPA2016D2 allows audio playback without I²C control. See Table 4 for entire default conditions.

There are several options to disable the amplifier:

• Write SPK_EN_R = 0 and SPK_EN_L = 0 to the register (0x01, 6 and 0x01, 7). This write disables each speaker amplifier, but leaves all other circuits operating.
• Write SWS = 1 to the register (0x01, 5). This action disables most of the amplifier functions.
• Apply V_IL to SDZ. This action shuts down all the circuits and has very low quiescent current consumption. This action resets the registers to its default values.

9.4.2 TPA2016D2 AGC Recommended Settings

9.5.1 General I²C Operation

The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. The bus transfers data serially one bit at a time. The address and data 8-bit bytes are transferred most significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. Figure 38 shows a typical sequence. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device, and then waits for an acknowledge condition. The TPA2016D2 holds SDA low during the acknowledge clock period to indicate acknowledgment. When this acknowledgment occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection.

An external pullup resistor must be used for the SDA and SCL signals to set the logic high level for the bus. When the bus level is 5 V, use pullup resistors between 1 kΩ and 2 kΩ.

Figure 38. Typical I²C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 38.

9.5.2 Single- and Multiple-Byte Transfers

The serial control interface supports both single-byte and multi-byte read or write operations for all registers.

During multiple-byte read operations, the TPA2016D2 responds with data, one byte at a time, starting at the register assigned, as long as the master device continues to respond with acknowledgments.

The TPA2016D2 supports sequential I²C addressing. For write transactions, if a register is issued followed by data for that register and all the remaining registers that follow, a sequential I²C write transaction has occurred. For I²C sequential write transactions, the register issued then serves as the starting point, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines the number of registers written.

9.5.3 Single-Byte Write

As Figure 39 shows, a single-byte data write transfer begins with the master device transmitting a start condition followed by the I²C device address and the read or write bit. The read or write bit determines the direction of the data transfer. For a write data transfer, the read/write bit must be set to '0'. After receiving the correct I²C device address and the read/write bit, the TPA2016D2 responds with an acknowledge bit. Next, the master transmits the register byte corresponding to the TPA2016D2 internal memory address being accessed. After receiving the register byte, the TPA2016D2 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the register byte, the TPA2016D2 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer.

Figure 39. Single-Byte Write Transfer

9.5.4 Multiple-Byte Write and Incremental Multiple-Byte Write

A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the TPA2016D2 as shown in Figure 40. After receiving each data byte, the TPA2016D2 responds with an acknowledge bit.

Figure 40. Multiple-Byte Write Transfer

9.5.5 Single-Byte Read

As Figure 41 shows, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I²C device address and the read or write bit. For the data read transfer, both a write followed by a read are actually executed. Initially, a write is executed to transfer the address byte of the internal memory address to be read. As a result, the read or write bit is set to a 0.

After receiving the TPA2016D2 address and the read or write bit, the TPA2016D2 responds with an acknowledge bit. The master then sends the internal memory address byte, after which the TPA2016D2 issues an acknowledge bit. The master device transmits another start condition followed by the TPA2016D2 address and the read or write bit again. This time the read/write bit is set to 1, indicating a read transfer. Next, the TPA2016D2 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.

Figure 41. Single-Byte Read Transfer

9.5.6 Multiple-Byte Read

A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TPA2016D2 to the master device as shown in Figure 42. With the exception of the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

Figure 42. Multiple-Byte Read Transfer

Table 3. TPA2016D2 Register Map

Table 4. TPA2016D2 Default Register Values Table

Table 5. IC Function Control (Address: 1)

Table 6. AGC Attack Control (Address: 2)

Table 7. AGC Release Control (Address: 3)

Table 8. AGC Hold Time Control (Address: 4)

Table 9. AGC Fixed Gain Control (Address: 5)

Table 10. AGC Control (Address: 6)

Table 11. AGC Control (Address: 7)