SLOS650F August   2009  – June 2016 TPA3113D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics, VCC = 24 V
    6. 6.6 DC Electrical Characteristics, VCC = 12 V
    7. 6.7 AC Electrical Characteristics, VCC = 24 V
    8. 6.8 AC Electrical Characteristics, VCC = 12 V
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gain Setting Through GAIN0 and GAIN1 Inputs
      2. 7.3.2 SD Operation
      3. 7.3.3 PLIMIT
      4. 7.3.4 GVDD Supply
      5. 7.3.5 DC Detect
      6. 7.3.6 PBTL Select
      7. 7.3.7 Short-Circuit Protection and Automatic Recovery Feature
      8. 7.3.8 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 TPA3113D2 Modulation Scheme
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Stereo Class-D Amplifier With BTL Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Ferrite Bead Filter Considerations
          2. 8.2.1.2.2 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
          3. 8.2.1.2.3 When to Use an Output Filter for EMI Suppression
          4. 8.2.1.2.4 Input Resistance
          5. 8.2.1.2.5 Input Capacitor, CI
          6. 8.2.1.2.6 BSN and BSP Capacitors
          7. 8.2.1.2.7 Differential Inputs
          8. 8.2.1.2.8 Using LOW-ESR Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Stereo Class-D Amplifier With BTL Output
      3. 8.2.3 Stereo Class-D Amplifier With PBTL Output
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Decoupling, CS
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Material Recommendation
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage AVCC, PVCC –0.3 30 V
VI Interface pin voltage SD, GAIN0, GAIN1, PBTL, FAULT (2) –0.3 VCC + 0.3 V
< 10 V/ms
PLIMIT –0.3 GVDD + 0.3 V
RINN, RINP, LINN, LINP –0.3 6.3 V
Continuous total power dissipation See Thermal Information
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature(3) –40 150 °C
RL Minimum load resistance BTL: PVCC > 15 V 4.8 Ω
BTL: PVCC ≤ 15 V 3.2
PBTL 3.2
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-kΩ resister in series with the pins.
(3) The TPA3113D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Briefs Quad Flatpack No-Lead Logic Packages for more information about using the TSSOP thermal pad.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(3) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)(4) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) In accordance with JEDEC Standard 22, Test Method A114-B.
(4) In accordance with JEDEC Standard 22, Test Method C101-A

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage PVCC, AVCC 8 26 V
VIH High-level input voltage SD, GAIN0, GAIN1, PBTL 2 V
VIL Low-level input voltage SD, GAIN0, GAIN1, PBTL 0.8 V
VOL Low-level output voltage FAULT, RPULLUP = 100k, VCC = 26 V 0.8 V
IIH High-level input current SD, GAIN0, GAIN1, PBTL, VI = 2 V, VCC = 18 V 50 µA
IIL Low-level input current SD, GAIN0, GAIN1, PBTL, VI = 0.8 V, VCC = 18 V 5 µA
TA Operating free-air temperature –40 85 °C

6.4 Thermal Information

THERMAL METRIC(1)(2) TPA3113D2 UNIT
PWP (TSSOP)
28 PINS
RθJA Junction-to-ambient thermal resistance 30.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 33.5 °C/W
RθJB Junction-to-board thermal resistance 17.5 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 7.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the application report Semiconductor and IC Package Thermal Metrics.
(2) For thermal estimates of this device based on PCB copper area, see the PCB Thermal Calculator.

6.5 DC Electrical Characteristics, VCC = 24 V

TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
| VOS | Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB 1.5 15 mV
ICC Quiescent supply current SD = 2 V, no load, PVCC = 24 V 32 50 mA
ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 24 V 250 400 µA
rDS(on) Drain-source ON-state resistance VCC = 12 V, IO = 500 mA,
TJ = 25°C		 High Side 400 mΩ
Low side 400
G Gain GAIN1 = 0.8 V GAIN0 = 0.8 V 19 20 21 dB
GAIN0 = 2 V 25 26 27
GAIN1 = 2 V GAIN0 = 0.8 V 31 32 33 dB
GAIN0 = 2 V 35 36 37
ton Turnon time SD = 2 V 14 ms
tOFF Turnoff time SD = 0.8 V 2 μs
GVDD Gate Drive Supply IGVDD = 100 μA 6.4 6.9 7.4 V
tDCDET DC Detect time V(RINN) = 6 V, VRINP = 0 V 420 ms

6.6 DC Electrical Characteristics, VCC = 12 V

TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
| VOS | Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB 1.5 15 mV
ICC Quiescent supply current SD = 2 V, no load, PVCC = 12 V 20 35 mA
ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 12 V 200 µA
rDS(on) Drain-source ON-state resistance VCC = 12 V, IO = 500 mA,
TJ = 25°C		 High Side 400 mΩ
Low side 400
G Gain GAIN1 = 0.8 V GAIN0 = 0.8 V 19 20 21 dB
GAIN0 = 2 V 25 26 27
GAIN1 = 2 V GAIN0 = 0.8 V 31 32 33 dB
GAIN0 = 2 V 35 36 37
tON Turnon time SD = 2 V 14 ms
tOFF Turnoff time SD = 0.8 V 2 μs
GVDD Gate Drive Supply IGVDD = 2 mA 6.4 6.9 7.4 V
VO Output Voltage maximum under PLIMIT control V(PLIMIT) = 2 V; VI = 1 Vrms 6.75 7.90 8.75 V

6.7 AC Electrical Characteristics, VCC = 24 V

TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
KSVR Power Supply ripple rejection 200 mVPP ripple at 1 kHz,
Gain = 20 dB, Inputs AC-coupled to AGND		 –70 dB
PO Continuous output power THD+N = 10%, f = 1 kHz, VCC = 10 V 6 W
THD+N Total harmonic distortion + noise VCC = 16 V, f = 1 kHz, PO = 3 W (half-power) 0.07%
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB 65 µV
–80 dBV
Crosstalk VO = 1 Vrms, Gain = 20 dB, f = 1 kHz –100 dB
SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted		 102 dB
fOSC Oscillator frequency 250 310 350 kHz
Thermal trip point 150 °C
Thermal hysteresis 15 °C

6.8 AC Electrical Characteristics, VCC = 12 V

TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
KSVR Supply ripple rejection 200 mVPP ripple from 20 Hz–1 kHz,
Gain = 20 dB, Inputs AC-coupled to AGND 		–70 dB
THD+N Total harmonic distortion + noise RL = 8 Ω, f = 1 kHz, PO = 3 W (half-power) 0.06%
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB 65 µV
–80 dBV
Crosstalk Po = 1 W, Gain = 20 dB, f = 1 kHz –100 dB
SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 20 dB, A-weighted		 102 dB
fOSC Oscillator frequency 250 310 350 kHz
Thermal trip point 150 °C
Thermal hysteresis 15 °C

6.9 Typical Characteristics

(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3113D2 EVM which is available at ti.com.)
TPA3113D2 g001_los528.gif
Figure 1. Total Harmonic Distortion vs Frequency (BTL)
TPA3113D2 g003_los650.gif
Figure 3. Total Harmonic Distortion vs Frequency (BTL)
TPA3113D2 g005_los650.gif
Figure 5. Total Harmonic Distortion vs Frequency (BTL)
TPA3113D2 g007_los528.gif
Figure 7. Total Harmonic Distortion + Noise vs Output Power (BTL)
TPA3113D2 g009_los528.gif
Figure 9. Total Harmonic Distortion + Noise vs Output Power (BTL)
TPA3113D2 g013_los528.gif
Dashed line represents thermally limited region.
Figure 11. Maximum Output Power vs PLIMIT Voltage (BTL)
TPA3113D2 g015_los528.gif
Figure 13. Gain/Phase vs Frequency (BTL)
TPA3113D2 g032_los528.gif
Dashed lines represent thermally limited region.
Figure 15. Efficiency vs Output Power (BTL With LC Filter)
TPA3113D2 g033_los528.gif
Dashed lines represent thermally limited region.
Figure 17. Efficiency vs Output Power (BTL With LC Filter)
TPA3113D2 g034_los528.gif
Dashed lines represent thermally limited region.
Figure 19. Efficiency vs Output Power (BTL With LC Filter)
TPA3113D2 g023_los528.gif
Figure 21. Crosstalk vs Frequency (BTL)
TPA3113D2 g025_los650.gif
Figure 23. Total Harmonic Distortion vs Frequency (PBTL)
TPA3113D2 g027_los528.gif
Figure 25. Gain/Phase vs Frequency (PBTL)
TPA3113D2 g030_los528.gif
Figure 27. Supply Current vs Output Power (PBTL)
TPA3113D2 g002_los650.gif
Figure 2. Total Harmonic Distortion vs Frequency (BTL)
TPA3113D2 g004_los528.gif
Figure 4. Total Harmonic Distortion vs Frequency (BTL)
TPA3113D2 g006_los650.gif
Figure 6. Total Harmonic Distortion vs Frequency (BTL)
TPA3113D2 g008_los528.gif
Figure 8. Total Harmonic Distortion + Noise vs Output Power (BTL)
TPA3113D2 g012_los528.gif
Figure 10. Total Harmonic Distortion + Noise vs Output Power (BTL)
TPA3113D2 g014_los528.gif
Dashed line represents thermally limited region.
Figure 12. Output Power vs PLIMIT Voltage (BTL)
TPA3113D2 g018_los528.gif
Dashed lines represent thermally limited region.
Figure 14. Efficiency vs Output Power (BTL)
TPA3113D2 g019_los528.gif
Dashed lines represent thermally limited region.
Figure 16. Efficiency vs Output Power (BTL)
TPA3113D2 g020_los528.gif
Dashed lines represent thermally limited region.
Figure 18. Efficiency vs Output Power (BTL)
TPA3113D2 g021_los528.gif
Dashed lines represent thermally limited region.
Figure 20. Supply Current vs Total Output Power (BTL)
TPA3113D2 g024_los528.gif
Figure 22. Supply Ripple Rejection Ratio vs Frequency (BTL)
TPA3113D2 g026_los650.gif
Figure 24. Total Harmonic Distortion + Noise vs Output Power (PBTL)
TPA3113D2 g029_los528.gif
Figure 26. Efficiency vs Output Power (PBTL)
TPA3113D2 g031_los528.gif
Figure 28. Supply Ripple Rejection Ratio vs Frequency (PBTL)