SLVSCF6F April   2014  – May 2019

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      TPD1S514 Family Circuit Protection Scheme
      2.      TPD1S514 Family Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Consumption
    6. 7.6  Electrical Characteristics EN Pin
    7. 7.7  Thermal Shutdown Feature
    8. 7.8  Electrical Characteristics nFET Switch
    9. 7.9  Electrical Characteristics OVP Circuit
    10. 7.10 Electrical Characteristics VBUS_POWER Circuit
    11. 7.11 Timing Requirements
    12. 7.12 TPD1S514-1 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Over Voltage Protection on VBUS_CON up to 30 V DC
      2. 8.3.2  Precision OVP (< ±1% Tolerance)
      3. 8.3.3  Low RON nFET Switch Supports Host and Charging Mode
      4. 8.3.4  VBUS_POWER, TPD1S514-1, TPD1S514-2, TPD1S514-3
      5. 8.3.5  VBUS_POWER, TPD1S514
      6. 8.3.6  Powering the System When Battery is Discharged
      7. 8.3.7  ±15 kV IEC 61000-4-2 Level 4 ESD Protection
      8. 8.3.8  100 V IEC 61000-4-5 µs Surge Protection
      9. 8.3.9  Startup and OVP Recovery Delay
      10. 8.3.10 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VBUS_CON < 3.5 V (Minimum VBUS_CON)
      2. 8.4.2 Operation With VBUS_CON > VOVP
      3. 8.4.3 OTG Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPD1S514-1 USB 2.0/3.0 Case 1: Always Enabled
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VBUS Voltage Range
          2. 9.2.1.2.2 Discharged Battery
        3. 9.2.1.3 Application Curves
      2. 9.2.2 TPD1S514-1 USB 2.0/3.0 Case 2: PMIC Controlled EN
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 VBUS Voltage Range
          2. 9.2.2.2.2 PMIC Power Requirement
          3. 9.2.2.2.3 Discharged Battery
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YZ|12
Thermal pad, mechanical data (Package|Pins)

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
IEC 61000-4-2 Contact Discharge VBUS_CON pin ±15000
IEC 61000-4-2 Air-gap Discharge VBUS_CON pin ±15000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.