SLLSEU8B March 2017 – May 2020 TPD2S703-Q1
PRODUCTION DATA.
When the VD+, or VD– voltages rise above VOVP, the internal nFET switches are turned off, protecting the transceiver from overvoltage conditions. The response is very rapid, with the FET switches turning off in less than 1 µs. Before the OVP condition, the FLT pin is High-Z, and is pulled HIGH via an external resistor to indicate there is no fault. Once the OVP condition occurs, the FLT pin is asserted LOW. When the VD+, or VD– voltages returns below VOVP – VHYS-OVP, the nFET switches are turned on again. When the OVP condition is cleared and the nFETs are completely turned on, the FLT is reset to high-Z.