SLLSEU8B March   2017  – May 2020 TPD2S703-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      USB 2.0 Port With Short-to-Battery and IEC ESD Protection
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings—AEC Specification
    3. 6.3  ESD Ratings—IEC Specification
    4. 6.4  ESD Ratings—ISO Specification
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Thermal Information
    7. 6.7  Electrical Characteristics
    8. 6.8  Power Supply and Supply Current Consumption Chracteristics
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 OVP Operation
      2. 8.3.2 OVP Threshold
      3. 8.3.3 D± Clamping Voltage
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Device Operation
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Common choke and Inductor for VD+ and VD-
        2. 9.2.2.2 VREF Operation
          1. 9.2.2.2.1 Mode 0
          2. 9.2.2.2.2 Mode 1
        3. 9.2.2.3 Mode 1 Enable Timing
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VPWR Path
    2. 10.2 VREF Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Power Supply and Supply Current Consumption Chracteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VUVLO_RISING_VPWR VPWR rising UVLO threshold Use standard mode 0 set-up. Set EN = 0 V, load D+ to 45 Ω, VD+ = 3.3 V. Set VPWR = 3.5 V, and step up VPWR until 90% of VD+ appears on D+ 3.7 3.95 4.2 V
VUVLO_HYST_VPWR VPWR UVLO hysteresis Use standard mode 0 set up. Set EN = 0 V, load D+ to 45 Ω, VD+ = 3.3 V. Set VPWR = 4.3 V, and step down VPWR until D+ falls to 10% of VD+. This gives VUVLO_FALLING_VPWR. VUVLO_RISING_VPWR – VUVLO_FALLING_VPWR = VUVLO_HYST_VPWR for this unit 250 300 400 mV
VUVLO_RISING_VREF VREF rising UVLO threshold in mode 0 Use standard mode 0 set up. Set EN = 0V, load D+ to 45 Ω, VD+ = 3.3 V. Set VREF = 2.5 V, and step up VREF until 90% of VD+ appears on D+ 2.6 2.7 2.9 V
VUVLO_HYST_VREF VREF UVLO hysteresis Use standard mode 0 set up. Set EN = 0 V, load D+ to 45 Ω, VD+ = 3.3 V. Set VREF = 3 V, and step down VREF until D+ falls to 10% of VD+. This gives VUVLO_FALLING_VREF. VUVLO_RISING_VREF –VUVLO_FALLING_VREF = VUVLO_HYST_VREF for this unit 75 125 200 mV
IVPWR_DISABLED_MODE0 VPWR disabled current consumption Use standard mode 0. EN = 5 V . Measure current into VPWR 110 µA
IVPWR_DISABLED_MODE1 VPWR disabled current consumption Use standard mode 1. EN = 5 V. Measure current into VPWR 110 µA
IVREF_DISABLED VREF disabled current consumption mode 0 Use standard mode 0. EN = 5 V. Measure current into VREF 10 µA
IVPWR_MODE0 VPWR pperating current consumption Use standard mode 0. EN = 0 V. Measure current into VPWR 250 µA
IVPWR_MODE1 VPWR operating current consumption Use standard mode 1. EN = 0 V. Measure current into VPWR 350 µA
IVREF VREF operating current consumption mode 0 Use standard mode 0. EN = 0 V. Measure current into VREF 12 20 µA
ICHG_VREF VREF fast charge current Standard mode 1. 0.1 µF < CVREF < 3 µF. Set-up for charging to 3.3 V. Use a high voltage capacitor that does not derate capacitance up the 3.3 V. Measure slope to calculate the current when CVREF cap is being charged. Test to check this OPEN LOOP method 22 mA
ID_OFF_LEAK_STB Mode 0. Measured flowing into D+ or D– supply, VPWR = 0 V, VD+ or VD– = 18 V, EN = 0 V, VREF = 0 V, D± = 0 V –1 1 µA
ID_ON_LEAK_STB Mode 0. Measured flowing into D+ or D– supply, VPWR = 5 V, VD+ or VD– = 18 V, EN = 0 V, VREF = 3.3 V, D± = 0 V –1 1 µA
IVD_OFF_LEAK_STB Mode 0. Measured flowing out of VD+ or VD– supply, VPWR = 0 V, VD+ or VD– = 18 V, EN = 0 V, VREF = 0 V, D± = 0 V 120
IVD_ON_LEAK_STB Mode 0. Measured flowing out of VD+ or VD– supply, VPWR = 5 V, VD+ or VD– = 18 V, EN = 0 V, VREF = 3.3 V, D± = 0 V 120 µA
IVPWR_TO_VREF_LEAK Leakage from VPWR to VREF Use standard mode 0.  Set VREF = 0 V.  Measured current flowing out of VREF pin 1 µA
IVREF_TO_VPWR_LEAK Leakage from VREF to VPWR Use standard mode 0.  Set VPWR = 0 V.  Measured as current flowing out of VPWR pin 1 µA