SLIS110C April   2003  – March 2015 TPIC8101

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Functional Terminal Description
        1. 8.3.1.1  Supply Voltage (VDD)
        2. 8.3.1.2  Ground (GND)
        3. 8.3.1.3  Reference Supply (Vref)
        4. 8.3.1.4  Buffered Integrator Output (OUT)
        5. 8.3.1.5  Integration/Hold Mode Selection (INT/HOLD)
        6. 8.3.1.6  Chip Select for SPI (CS)
        7. 8.3.1.7  Oscillator Input (XIN)
        8. 8.3.1.8  Oscillator Output (XOUT)
        9. 8.3.1.9  Data Output (SDO)
        10. 8.3.1.10 Data Input (SDI)
        11. 8.3.1.11 Serial Clock (SCLK)
        12. 8.3.1.12 Test (TEST)
        13. 8.3.1.13 Feedback Output for Amplifiers (CH1FB and CH2FB)
        14. 8.3.1.14 Input Amplifiers (CH1P, CH1N, CH2P, and CH2N)
      2. 8.3.2 Timing Information
    4. 8.4 Device Functional Modes
      1. 8.4.1 System Transfer Equation
      2. 8.4.2 Programming in Normal Mode (TEST = 1)
      3. 8.4.3 Default SPI Mode
      4. 8.4.4 Advanced SPI Mode
      5. 8.4.5 Digital Data Output from the TPIC8101
    5. 8.5 Programming
      1. 8.5.1 Programming Examples
      2. 8.5.2 Programming in TEST Mode (TEST = 0)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The TPIC8101 is designed for knock sensor signal conditioning in automotive applications. The device is an analog interface between the engine acoustical sensors or accelerometers and the fuel management systems of a gasoline engine. The two wide-band amplifiers process signals from the piezoelectric sensors. Outputs of the amplifiers feed a channel select MUX switch and then a third-order antialiasing filter. This signal is converted using an analog-to-digital conversion (10 bits with a sampling frequency of 200 kHz) prior to the gain stage.

8.2 Functional Block Diagram

TPIC8101 fbd_slis110.gif

8.3 Feature Description

The gain stage is adjustable through the SPI to compensate for the knock energies. The gain setting is selectable up to 64 values ranging from 0.111 to 2.0.

The output of the gain stage feeds a band-pass filter circuit to process the particular frequency component associated with the engine and transducer.

The band-pass filter has a gain of two and a center frequency range between 1.22 and 19.98 kHz (64-bit selection). The output from this stage is internally clamped.

The output from the band-pass filter is full-wave rectified with its output clamped below VDD.

The full-wave rectified signals are integrated using an integrator time constant set by the SPI and integration time window set by the pulse duration of INT/HOLD. At the start of each knock window, the integrator output is reset. The output of the integrator is internally clamped and the digital output may be directly interfaced to the microprocessor.

The integrated signal is converted to an analog format by a 10-bit DAC. The microprocessor may interface to this signal, read this data, and adjust the spark ignition timing to optimize fuel efficiency related to load versus engine RPM.

8.3.1 Functional Terminal Description

8.3.1.1 Supply Voltage (VDD)

The VDD terminal is the input supply for the IC, typically 5-V ±5% tolerant. A noise filter capacitor of 4.7 µF (typical) is required on this terminal to ensure stability of the internal circuits.

8.3.1.2 Ground (GND)

The GND terminal is connected to the system ground rail.

8.3.1.3 Reference Supply (Vref)

The Vref is an internally generated supply reference voltage for biasing the amplifier inputs. The terminal is used to decouple any noise in the system by placing an external capacitor of 22 nF (typical).

8.3.1.4 Buffered Integrator Output (OUT)

The OUT terminal is the output of the integrated signal. This is an analog signal interfaced to the microprocessor A/D channel for data acquisition. A capacitor of 2.2 nF is used to stabilize the signal output.

8.3.1.5 Integration/Hold Mode Selection (INT/HOLD)

The INT/HOLD is an input control signal from the microprocessor to select either to integrate the sensed signal or to hold the data for acquisition. There is an internal pulldown on this terminal (default HOLD mode).

8.3.1.6 Chip Select for SPI (CS)

The CS terminal allows serial communication to the IC through the SPI from a master controller. The chip select is active low with an internal pullup (default inactive).

8.3.1.7 Oscillator Input (XIN)

The XIN terminal is the input to the inverter used for the oscillator circuit. An external clock signal from the MCU, crystal, or ceramic resonator is configured with resistors and capacitors. To bias the inverter, place a resistor (1 MΩ typical) across XIN and XOUT.

This clock signal is prescaled to set the internal sampling frequency of the A/D converter.

8.3.1.8 Oscillator Output (XOUT)

The XOUT terminal is the output of the inverter used for the oscillator circuit.

8.3.1.9 Data Output (SDO)

The SDO output is the SPI data bus reporting information back to the microprocessor. This is a tri-state output with the output set to high-impedance mode when CS is pulled to VDD. The high-impedance state can also be programmed by setting a bit in the prescale word, which takes precedence over the CS setting. The output is disabled when the CS terminal is pulled high (VDD).

8.3.1.10 Data Input (SDI)

The SDI terminal is the communication interface for data transfer between the master and slave components. The SDI has an internal pullup to VDD; the data stream is in 8-bit word format.

8.3.1.11 Serial Clock (SCLK)

The SCLK output signal is used for synchronous communication of data. Typically, the output from the master clock is low with the IC having an internal pullup resistor to VDD. The data is clocked to the internal shift register on the falling clock edge.

8.3.1.12 Test (TEST)

The TEST terminal, when pulled low, allows the IC to enter the test mode. During normal operation, this terminal is left open or tied high (VDD). There is an internal pullup to VDD (default).

8.3.1.13 Feedback Output for Amplifiers (CH1FB and CH2FB)

The CHXFB are amplifier outputs for the sensor signals. The gain of the respective amplifiers is set using the CHXFB and CHX input terminals (see Figure 1).

8.3.1.14 Input Amplifiers (CH1P, CH1N, CH2P, and CH2N)

CH1P, CH1N, CH2P, and CH2N are the inputs for the two amplifiers which interface to the external knock sensors.

The gain is set by external resistors R1 and R2. The inputs and outputs of the amplifier are rail-to-rail compatible to the supply VDD.

An internal multiplexer selects the desired sensor signal to process, which is programmable through the SPI.

TPIC8101 sch_input_signal_conf_slis110.gif

NOTE:

The series capacitor C is not mandatory and may be removed in some application circuits
Figure 4. Input Signal Configuration

8.3.2 Timing Information

This is an 8-bit SPI protocol used to communicate with the microcontroller in the system for setting various operating parameters.

When CS is held high, the signals on the SCLK and SDI lines are ignored and SDO is forced into a high-impedance state. SCLK must be low when CS is asserted low.

On each falling edge of the SCLK pulse after CS is asserted low, the new byte is serially shifted into the register. The most significant bit (MSB) is shifted first. Only eight bits in a frame are acceptable. When a number of bits shifted varies from the value eight, the information is ignored and the register retains the old setting.

The shift register transfers the data into a latch register after the eighth SCLK clock pulse and when CS transitions from low to high (see Figure 1).

The function of the integration mode is to ignore any SPI frame transmission when the INT/HOLD bit = 1. In the hold mode with INT/HOLD = 0, all necessary bytes may be transmitted.

8.4 Device Functional Modes

8.4.1 System Transfer Equation

The output voltage may be derived from:

Equation 1. TPIC8101 Eq01_VO_slis110.gif

where

  • VIN = Input voltage peak (amplitude)
  • VO = Output voltage
  • AIN = Input amplifier gain setting
  • AP = Programmable gain setting
  • ABP = Gain of band-pass filter
  • AINT = Gain of integrator
  • tINT = Integration time from 0.5 to 10 ms
  • AO = Output buffer gain
  • τC = Programmable integrator time constant
  • VRESET = Reset voltage from which the integration operation starts

If ABP = AINT = 2 and AIN = AO = 1, then:

Equation 2. TPIC8101 Eq02_vo_slis110.gif

8.4.2 Programming in Normal Mode (TEST = 1)

To enable programming in the normal mode, the TEST terminal must be high. Communication is through the SPI and the CS terminal is used to enable the IC. The information on the SDI line consists of two parts: address and data.

After power up, the SPI is in default mode (see Table 1).

8.4.3 Default SPI Mode

The SPI is in the default mode on the power-up sequence. In this case, the SDO directly equals the SDI (echo function). In this mode, five commands can be transmitted by the master controller to configure the IC (see Table 1).

Table 1. Default SPI Mode

NO. Code Command (t) Data Response (t)
1 010 D[4:0] Set the prescaler and SDO status OSCIN frequency
D[4:1] = 0000 → 4 MHz
D[4:1] = 0001 → 5 MHz
D[4:1] = 0010 → 6 MHz
D[4:1] = 0011 → 8 MHz
D[4:1] = 0100 → 10 MHz
D[4:1] = 0101 → 12 MHz
D[4:1] = 0110 → 16 MHz
D[4:1] = 0111 → 20 MHz
D[4:1] = 1000 → 24 MHz		 SDI
(010 D[4:0])
D[0] = 0 → SDO active
D[1] = 1 → SDO high impedance
2 1110 000 D[0] Select the channel D[0] = 0 → Channel 1 selected
D[1] = 1 → Channel 2 selected		 SDI
(1110 000 D[0])
3 00 D[5:0] Set the band-pass center frequency D[5:0] (see Table 3) SDI
(00 D[5:0])
4 10 D[5:0] Set the gain D[5:0] (see Table 3) SDI
(10 D[5:0])
5 110 D[4:0] Set the integration time constant D[4:0] (see Table 3) SDI
(100 D[4:0])
6 0111 0001 Set SPI configuration to the advanced mode(1) None SDI
(0111 0001)
(1) Command number 6 is to enter into the advanced mode.

8.4.4 Advanced SPI Mode

The advanced SPI mode has additional features to the default SPI mode. A control byte is written to the SDI and shifted with the MSB first. The response byte on the SDO is shifted out with the MSB first. The response byte corresponds to the previous command. Therefore, the SDI shifts in a control byte n and shifts out a response command byte n − 1. Each control/response pair of commands requires two full 8-bit shift cycles to complete a transmission. Table 2 shows the control bytes with the expected response.

In the advanced SPI mode, only a power-down condition may reset the SPI mode to the default state on the subsequent power-up cycle.

Table 2. Advanced SPI Mode Control Bytes and Expected Response

NO. Code Command (t) Data Response (t)
1 010 D[4:0] Set the prescaler and SDO status OSCIN frequency
D[4:1] = 0000 → 4 MHz
D[4:1] = 0001 → 5 MHz
D[4:1] = 0010 → 6 MHz
D[4:1] = 0011 → 8 MHz
D[4:1] = 0100 → 10 MHz
D[4:1] = 0101 → 12 MHz
D[4:1] = 0110 → 16 MHz
D[4:1] = 0111 → 20 MHz
D[4:1] = 1000 → 24 MHz		 Byte 1 (D7 to D0) of the digital integrator output
D[0] = 0 → SDO active
D[1] = 1 → SDO high impedance
2 1110 000 D[0] Select the channel D[0] = 0 → Channel 1 selected
D[1] = 1 → Channel 2 selected		 D9 to D8 of digital integrator output followed by six zeros
3 00 D[5:0] Set the band-pass center frequency D[5:0] (see Table 3) Byte 1 (MSB) of the 00000001
4 10 D[5:0] Set the gain D[5:0] (see Table 3) Byte 2 (LSB) 11100000
5 110 D[4:0] Set the integration time constant D[4:0] (see Table 3) SPI configuration (MSB) 01110001(LSB)
6 0111 0001 Set SPI configuration to the advanced mode None Inverted SPI configuration (MSB)10001110(LSB)

8.4.5 Digital Data Output from the TPIC8101

Digital output:

  • Digital integrator output (10 bits, D[9:0])
  • First response byte (MSB): 8 bits for D7 to D0 of the integrator output
  • Second response byte (LSB): 2 bits for D9 to D8 of the integrator output followed by six zeros

8.5 Programming

Table 3. Integrator Programming

Decimal Value
(D4:D0)		 Integrator Time Constant
(µs)		 Band-Pass Frequency
(kHz)		 Gain Decimal Value
(D5:D0)		 Band-Pass Frequency
(kHz)		 Gain
0 40 1.22 2 32 4.95 0.421
1 45 1.26 1.882 33 5.12 0.4
2 50 1.31 1.778 34 5.29 0.381
3 55 1.35 1.684 35 5.48 0.364
4 60 1.4 1.6 36 5.68 0.348
5 65 1.45 1.523 37 5.9 0.333
6 70 1.51 1.455 38 6.12 0.32
7 75 1.57 1.391 39 6.37 0.308
8 80 1.63 1.333 40 6.64 0.296
9 90 1.71 1.28 41 6.94 0.286
10 100 1.78 1.231 42 7.27 0.276
11 110 1.87 1.185 43 7.63 0.267
12 120 1.96 1.143 44 8.02 0.258
13 130 2.07 1.063 45 8.46 0.25
14 140 2.18 1 46 8.95 0.236
15 150 2.31 0.944 47 9.5 0.222
16 160 2.46 0.895 48 10.12 0.211
17 180 2.54 0.85 49 10.46 0.2
18 200 2.62 0.81 50 10.83 0.19
19 220 2.71 0.773 51 11.22 0.182
20 240 2.81 0.739 52 11.65 0.174
21 260 2.92 0.708 53 12.1 0.167
22 280 3.03 0.68 54 12.6 0.16
23 300 3.15 0.654 55 13.14 0.154
24 320 3.28 0.63 56 13.72 0.148
25 360 3.43 0.607 57 14.36 0.143
26 400 3.59 0.586 58 15.07 0.138
27 440 3.76 0.567 59 15.84 0.133
28 480 3.95 0.548 60 16.71 0.129
29 520 4.16 0.5 61 17.67 0.125
30 560 4.39 0.471 62 18.76 0.118
31 600 4.66 0.444 63 19.98 0.111

8.5.1 Programming Examples

  • Prescaler/SDO status:
    • 01000101 programs an input frequency of 6 MHz with SDO terminal in high impedance.
  • Channel selection:
    • 1110001 selects channel 2.
  • Band-pass frequency:
    • 00100111 programs a band-pass filter with center frequency of 6.37 kHz.
  • Gain control:
    • 10010100 programs the gain with attenuation of 0.739.
  • Integrator time constant:
    • 11000011 programs integrator time constant of 55 µs. Table 1 through Table 3 show the binary values.

8.5.2 Programming in TEST Mode (TEST = 0)

To enter test mode, the TEST terminal must be low. See Table 4 for the signal that may be accessed in this mode.

Table 4. Programming in TEST Mode

NO. Test Description SDI Command MSB, LSB Response Description
T1 AAF individual test 1111, 0000 ADC clock Deactivates the input and output operational amplifiers
AAF input connected to CH1FB terminal
AAF output connected to OUT terminal
T2 In-line test to AAF output 1111, 0000 None Deactivates the output operational amplifier
AAF output connected to OUT terminal
T3 Output buffer individual test 1111, 0010 None Opens the feedback loop of the output buffer and deactivates the input operational amplifier and AAF
CH1FB connected to positive input terminal of operational amplifier
CH2FB connected to negative input terminal of operational amplifier
T4 ADC/DAC individual test (with the output buffer) 1111, 0011 ADC data Deactivates the input operational amplifiers and AAF INT/HOLD = ADC_Sync
OSCIN = ADC_SCLK
DAC shifted in from SDI terminal
T5 ADC/DAC individual test (without the output buffer) 1111, 0100 ADC data Deactivates the input operational amplifiers, AAF, and output buffer
INT/HOLD = ADC_Sync
OSCIN = ADC_SCLK
DAC is shifted in from SDI terminal
T6 In-line test to ADC output 1111, 0011 ADC data INT/HOLD = ADC_Sync
OSCIN = ADC_SCLK
DAC shifted in from SDI terminal
T7 Reading of digital clamp flag 1111, 1000 Clamp flag D[2:0] Implies command number 6 (advanced SPI mode)
D[0]: Gain stage clamp status
D[1]: BPF stage clamp status
D[2]: INT stage clamp status
D = 0 → No clamp activated
D = 1 → Clamp activated