SLVSEG3E September   2019  – March 2022 TPS25840-Q1 , TPS25842-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Buck Regulator
      2. 10.3.2  Enable/UVLO
      3. 10.3.3  Switching Frequency and Synchronization (RT/SYNC)
      4. 10.3.4  Spread-Spectrum Operation
      5. 10.3.5  VCC, VCC_UVLO
      6. 10.3.6  Minimum ON-time, Minimum OFF-time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Bootstrap Voltage (BOOT)
      9. 10.3.9  RSNS, RSET, RILIMIT and RIMON
      10. 10.3.10 Overcurrent and Short Circuit Protection
        1. 10.3.10.1 Current Limit Setting using RILIMIT
        2. 10.3.10.2 Buck Average Current Limit Design Example
        3. 10.3.10.3 External MOSFET Gate Drivers
        4. 10.3.10.4 Cycle-by-Cycle Buck Current Limit
      11. 10.3.11 Overvoltage, IEC and Short-to-Battery Protection
        1. 10.3.11.1 V BUS and V CSN/OUT Overvoltage Protection
        2. 10.3.11.2 DP_IN and DM_IN Protection
      12. 10.3.12 Cable Compensation
        1. 10.3.12.1 Cable Compensation Design Example
      13. 10.3.13 USB Port Control
      14. 10.3.14 FAULT Response
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 Device Power Pins (IN, CSN/OUT, and PGND)
      17. 10.3.17 Thermal Shutdown
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
      3. 10.4.3 Device Truth Table (TT)
      4. 10.4.4 USB Port Operating Modes
        1. 10.4.4.1 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
        2. 10.4.4.2 Charging Downstream Port (CDP) Mode
        3. 10.4.4.3 Client Mode
      5. 10.4.5 High-bandwidth Data-line Switches
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1  Output Voltage
        2. 11.2.2.2  Switching Frequency
        3. 11.2.2.3  Inductor Selection
        4. 11.2.2.4  Output Capacitor Selection
        5. 11.2.2.5  Input Capacitor Selection
        6. 11.2.2.6  Bootstrap Capacitor Selection
        7. 11.2.2.7  VCC Capacitor Selection
        8. 11.2.2.8  Enable and Under Voltage Lockout Set-Point
        9. 11.2.2.9  Current Limit Set-Point
        10. 11.2.2.10 Cable Compensation Set-Point
        11. 11.2.2.11 FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Ground Plane and Thermal Considerations
    3. 13.3 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Related Links
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 Support Resources
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

Layout is a critical portion of good power supply design. The following guidelines help users design a PCB with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI. For more detailed EMC design consideration and test report, please see the PCB Layout and Parameters Recommendation for TPS2583X EMC Performance application report.

  1. Input capacitor: The input bypass capacitor, CIN, must be placed as close as possible to the IN and PGND pins. Grounding for both the input and output capacitors must consist of localized top side planes that connect to the PGND pin and PAD. A combination of different values and packages of capacitors can help improve the EMC performance (for example: 10 μF + 0.1 μF + 2.2 nF). Besides, the distance between the input filter section and the output power section must be at least 15mm to prevent the output high-frequency signal from coupling into the input filter. A 10-µF cap cross VIN and PGND pin on top of SW is suggested for TPS2584x-Q1.
  2. VCC bypass capacitor: Place bypass capacitors for VCC close to the VCC pin and ground the bypass capacitor to device ground.
  3. Use a ground plane in one of the middle layers as noise shielding and heat dissipation path.
  4. Connect the thermal pad to the ground plane. The QFN package has a thermal pad (PAD) connection that must be soldered down to the PCB ground plane. This pad acts as a heat-sink connection. The integrity of this solder connection has a direct bearing on the total effective RθJA of the application.
  5. Make VIN, VOUT and ground bus connections as wide as possible. This action reduces any voltage drops on the input or output paths of the converter and maximizes efficiency.
  6. Provide enough PCB area for proper heat sinking. As stated in the section, enough copper area must be used to ensure a low RθJA, commensurate with the maximum load current and ambient temperature. Make the top and bottom PCB layers with 2-ounce copper and no less than one ounce. Use an array of heat-sinking vias to connect the thermal pad (PAD) to the ground plane on the bottom PCB layer. If the PCB design uses multiple copper layers (recommended), thermal vias can also be connected to the inner layer heat-spreading ground planes.
  7. The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load current without excessive heating. Short, thick traces or copper pours (shapes) bring a high current conduction capacity to minimize parasitic resistance, but also cause a larger parasitic capacitance. Thus a balance must be found between smaller parasitic resistance and larger parasitic capacitance. And the current path must be kept straight forward to the inductor, otherwise the L-shaped or T-shaped path makes a sudden change of the impedance which causes signal reflection and impacts the performance of EMC. The output capacitors must be placed close to the VOUT end of the inductor and closely grounded to PGND pin and exposed PAD. Besides, do not punch vias on SW lines. Using shielded inductors or molded inductors to reduce high-frequency radiation.
  8. Sense and Set Resistors: The RSNS and RSET resistors connect to the current sense amplifier inputs at the CSP and CSN/OUT pins. For best current limit and cable compensation accuracy; short, parallel traces give the best performance. If it is not possible to place RSNS and RSET near the CSP and CSN/OUT pins, TI recommends that the traces from sense resistor be routed in parallel and of similar lengths. A small filter capacitor in parallel with RSNS and a small filter capacitor from CSN/OUT to AGND help decouple noise.
  9. RILIMIT and RIMON resistors must be placed as close as possible to the ILIMIT and IMON pins and connected to AGND. If needed, these components can be placed on the bottom side of the PCB with signals routed through small vias.
  10. Trace routing of DP_IN, DM_IN, DP_OUT, and DM_OUT: Route these traces as micro-strips with nominal differential impedance of 90 Ω. Minimize the use of vias in the high-speed data lines. Keep the reference GND plane devoid from cuts or splits above the differential pairs to prevent impedance discontinuities.
  11. FAULT are open-drain outputs. They can be connected to the VCC pin via pull-up resistors. Suggested resistor value is 100 kΩ.
  12. The area enclosed by current loop of input side and output side must be as small as possible; the area enclosed by the BOOT circuit must be as small as possible.
  13. Power ground PGND and the signal ground AGND must be separated in the actual PCB layout.