SLUS710E May   2006  – January 2024 TPS28225

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Undervoltage Lockout (UVLO)
      2. 6.3.2 Output Active Low
      3. 6.3.3 Enable/Power Good
      4. 6.3.4 3-State Input
        1. 6.3.4.1 TPS28225 3-State Exit Mode
        2. 6.3.4.2 External Resistor Interference
      5. 6.3.5 Bootstrap Diode
      6. 6.3.6 Upper and Lower Gate Drivers
      7. 6.3.7 Dead-Time Control
      8. 6.3.8 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Four Phases Driven by TPS28225 Driver
        2. 7.2.2.2 Switching The MOSFETs
        3. 7.2.2.3 List of Materials
      3. 7.2.3 Application Curves
    3. 7.3 System Examples
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

VDD = 7.2 V, EN/PG pulled up to VDD by 100-kΩ resistor, TA = TJ = –40°C to 125°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
UNDER VOLTAGE LOCKOUT
Rising thresholdVPWM = 0 V3.23.53.8V
Falling thresholdVPWM = 0 V2.73.0V
Hysteresis0.5V
BIAS CURRENTS
IDD(off)Bias supply currentVEN/PG = low, PWM pin floating350μA
IDDBias supply currentVEN/PG = high, PWM pin floating500μA
INPUT (PWM)
IPWMInput currentVPWM = 5 V185μA
VPWM = 0 V–200μA
PWM 3-state rising threshold(2)1.0V
PWM 3-state falling thresholdVPWM PEAK = 5 V3.43.84.0V
tHLD_R3-state shutdown Hold-off time250ns
TMINPWM minimum pulse to force UGATE pulseCL = 3 nF at UGATE , VPWM = 5 V30ns
ENABLE/POWER GOOD (EN/PG)
Enable high rising thresholdPG FET OFF1.72.1V
Enable low falling thresholdPG FET OFF0.81.0V
Hysteresis0.350.70V
Power good outputVDD = 2.5 V0.2V
UPPER GATE DRIVER OUTPUT (UGATE)
Source resistance500 mA source current1.02.0Ω
Source current (2)VUGATE-PHASE = 2.5 V2.0A
tRURise timeCL = 3 nF10ns
Sink resistance500 mA sink current1.02.0Ω
Sink current (2)VUGATE-PHASE = 2.5 V2.0A
tFUFall timeCL = 3 nF10ns
LOWER GATE DRIVER OUTPUT (LGATE)
Source resistance500 mA source current1.02.0Ω
Source current(2)VLGATE = 2.5 V2.0A
tRLRise time(2)CL = 3 nF10ns
Sink resistance500 mA sink current0.41.0Ω
Sink current(2)VLGATE = 2.5 V4.0A
Fall time(2)CL = 3 nF5ns
BOOTSTRAP DIODE
VFForward voltageForward bias current 100 mA1.0V
THERMAL SHUTDOWN
Rising threshold(2)150160170°C
Falling threshold(2)130140150°C
Hysteresis20°C
(1) Typical values for TA = 25°C
(2) Not production tested.