SLUS658D July   2005  – June 2019 TPS40190

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Dissipation Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internally Fixed Parameters
      2. 7.3.2 Output Short Circuit Protection
      3. 7.3.3 Enable Functionality
      4. 7.3.4 5-V Regulator
      5. 7.3.5 Startup Sequence and Timing
      6. 7.3.6 Prebias Outputs
  8. 8 Application and Implementation
    1. 8.1 Typical Applications
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Community Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRC|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Electrical Characteristics

TA = –40°C to 85°C, VVDD= 12 Vdc, TA =TJ, and all parameters at zero power dissipation (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VFB Feedback voltage range 0°C ≤ TJ ≤ 85°C 585 591 597 mV
-40°C ≤ TJ ≤ 85°C 582 591 597
INPUT SUPPLY
VVDD Input voltage range 4.5 15.0 V
IVDD Operating current VENABLE = 2.5 V, Outputs switching 2.5 mA
VENABLE = 0.6 V 20 μA
ON BOARD REGULATOR
V5VBP Output voltage VVDD > 6 V, I5VBP ≤ 10 mA 5.1 5.3 5.5 V
VDO Regulator dropout voltage VVDD - VBP5 , VVDD = 5 V, IBP5 ≤ 25 mA 270 400 mV
ISC Regulator current limit threshold 40 mA
IBP5 Average current(2) 40
OSCILLATOR
fSW Switching frequency 240 300 360 kHz
VRMP Ramp amplitude(1) 0.75 V
VVALLEY Valley voltage(1) 0.5 V
PWM
DMAX Maximum duty cycle(1) 85%
tON(min) Minimum controlled pulse(1) 130 ns
tDEAD Output driver dead time HDRV off to LDRV on 50 ns
LDRV off to HDRV on 25
SOFT-START
tSS Soft-start time 3.0 4.7 7.0 ms
tSSDLY Soft-start delay time(3) 6 ms
tREG Time to regulation 10.5 ms
ERROR AMPLIFIER
GBWP Gain bandwidth product(1) 5 MHz
AOL DC gain(1) 60 dB
IIB Input bias current (current out of FB pin) 100 0 nA
IEAOP Output source current VFB = 0 V 1 mA
IEAOM Output sink current VFB = 2 V 1 mA
SHORT CIRCUIT PROTECTION
tPSS(min) Minimum pulse during short circuit(1) 250 ns
tBLNK Blanking time(1) 100 140 180 ns
tOFF Off-time between restart attempts 25 95 ms
VILIM Short circuit comparator threshold voltage RCOMP(GND) = OPEN, TJ = 25°C 256 320 384 mV
RCOMP(GND) = 4 kΩ, TJ = 25°C 128 160 192
RCOMP(GND) = 12 kΩ, TJ = 25°C 368 460 552
OUTPUT DRIVERS
RHDHI High-side driver pull-up resistance VBOOT - VSW = 4.5 V, IHDRV = -100 mA 3 6 Ω
RHDLO High-side driver pull-down resistance VBOOT - VSW = 4.5 V, IHDRV = 100 mA 1.5 3 Ω
RLDHI Low-side driver pull-up resistance ILDRV = -100 mA 2.5 5 Ω
RLDLO Low-side driver pull-down resistance ILDRV = 100 mA 0.8 1.5 Ω
tHRISE High-side driver rise time(1) CLOAD = 1 nF 15 35 ns
tHFALL High-side driver fall time(1) CLOAD = 1 nF 10 25 ns
tLRISE Low-side driver rise time(1) CLOAD = 1 nF 15 35 ns
tLFALL Low-side driver fall time(1) CLOAD = 1 nF 10 25 ns
UNDERVOLTAGE LOCKOUT (UVLO)
VUVLO Turn-on voltage 4.1 4.25 4.4 V
UVLOHYST Hysteresis 270 320 370 mV
SHUTDOWN
VIH High-level input voltage ENABLE 2.8 V
VIL Low-level input votlage ENABLE 0.6 V
BOOT DIODE
VDFWD Bootstrap diode forward voltage IBOOT = 5 mA 0.6 0.8 1.2 V
(1) Specified by design. Not production tested.
(2) 40 mA is the current available for MOSFET gate drive, the device itself and any external loads. The sum of these must not exceed 40 mA.
(3) The delay time is the time delay from application of power to the device or from assertion of ENABLE until the output begins to rise.