SLVSAE6A July   2010  – August 2014 TPS53129

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematics
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
  8. 8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 PWM Operation
      2. 9.3.2 Light-Load Condition
      3. 9.3.3 Drivers
      4. 9.3.4 PWM Frequency and Adaptive On-Time Control
      5. 9.3.5 5-Volt Regulator
      6. 9.3.6 Soft Start
      7. 9.3.7 Pre-Bias Support
    4. 9.4 Device Functional Modes
      1. 9.4.1 Output Discharge Control
      2. 9.4.2 Over Current Limit
      3. 9.4.3 Over/Under Voltage Protection
      4. 9.4.4 UVLO Protection
      5. 9.4.5 Thermal Shutdown
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Typical Application Circuits
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design Procedure
      4. 10.2.4 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Suggestions
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Application and Implementation

10.1 Application Information

The TPS53129 is a Dual D-CAP2™ Mode control step-down controller in a realistic cost-sensitive application, that provides both a low core-type 1.05 V and I/O type 1.8 V output from a loosely regulated 12 V source. Ideal applications include: digital TV power supplies, networking home pins, digital set-top boxes (STB), DVD players and recorders, and gaming consoles.

10.2 Typical Application

10.2.1 Typical Application Circuits

TPS53129 qfn4_lvsae6.gif Figure 6. QFN
TPS53129 tssop1_lvsae6.gif Figure 7. TSSOP

10.2.2 Design Requirements

Table 1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage 12 V
Output voltage

Vo1 = 1.8 V, Vo2 = 1.05 V

10.2.3 Detailed Design Procedure

  1. Choose inductor.

    2. The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load. Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.

    Equation 4 can be used to calculate L1.

    Equation 4. TPS53129 eq4_lvsae6.gif

    The inductors current ratings needs to support both the RMS (thermal) current and the Peak (saturation) current. The RMS and peak inductor current can be estimated as follows.

    Equation 5. TPS53129 eq4a_lvs947.gif
    Equation 6. TPS53129 eq5a_lvs947.gif
    Equation 7. TPS53129 eq6a_lvs947.gif

    Note: The calculation above shall serve as a general reference. To further improve transient response, the output inductance could be reduced further. This needs to be considered along with the selection of the output capacitor.

  2. Choose output capacitor.

    3. The capacitor value and ESR determines the amount of output voltage ripple and load transient response. it is recommended to use a ceramic output capacitor.

    Equation 8. TPS53129 eq7a_lvs947.gif
    Equation 9. TPS53129 eq8a_lvs947.gif
    Equation 10. TPS53129 eq9b_lvs947.gif

    Where

    Equation 11. TPS53129 eq10a_lvs947.gif

    Select the capacitance value greater than the largest value calculated from Equation 8, Equation 9 and Equation 10. The capacitance for C1 should be greater than 66 μF.

    Where

    ΔVOS = The allowable amount of overshoot voltage in load transition

    ΔVUS = The allowable amount of undershoot voltage in load transition

    Tmin(off) = Minimum off time

  3. Choose input capacitor.

    4. The TPS53129 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A minimum 10-μF high-quality ceramic capacitor is recommended for the input capacitor. The capacitor voltage rating needs to be greater than the maximum input voltage.

  4. Choose bootstrap capacitor.

    5. The TPS53129 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the high-side drivers. A minimum 0.1-μF high-quality ceramic capacitor is recommended. The voltage rating should be greater than 10 V.

  5. Choose VREG5 and V5FILT capacitor.

    6. The TPS53129 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-μF high-quality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A minimum 1-μF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper operation. Both of these capacitors’ voltage ratings should be greater than 10 V.

  6. Choose output voltage divider resistors.

    7. The output voltage is set with a resistor divider from the output voltage node to the VFBx pin. It is recommended to use 1% tolerance or better resisters. Select R2 between 10 kΩ and 100 kΩ and use Equation 12 or Equation 13 to calculate R1.

    Equation 12. TPS53129 eq_11z_lvs947.gif
    Equation 13. TPS53129 eq11a1_lvs947.gif

    Where

    VFB(RIPPLE) = Ripple voltage at VFB

    Vswinj = Ripple voltage at error comparator

  7. Choose register setting for over current limit.
    8. Equation 14. TPS53129 eq12a_lvs947.gif
    Equation 15. TPS53129 eq13a_lvs947.gif

    Where

    RDS(ON) = Low side FET on-resistance

    ITRIP(min) = TRIP pin source current （8.5 μA）

    VOCL0ff = Minimum over current limit offset voltage (–20 mV)

    IOCL = Over current limit

  8. Choose soft start capacitor.

    9. Soft start time equation is as follows.

    Equation 16. TPS53129 eq14_lvs947.gif

10.2.4 Application Curves

TPS53129 fsw18_lvsae6.gif
A.
IO1 = 3 A
Figure 8. Switching Frequency vs Input Voltage (CH1)
TPS53129 fsw18vio_lvsae6.gif
A.
vO1 = 1.8 V
Figure 10. Switching Frequency vs Output Current (CH1)
TPS53129 vo18vio_lvsae6.gif
A.
VIN = 12 V vO1 = 1.8 V
Figure 12. Output Voltage vs Output Current (CH1)
TPS53129 vovi18_lvsae6.gif
A.
VIN = 12 V vO1 = 1.8 V
Figure 14. Output Voltage vs Input Voltage (CH1)
TPS53129 load18_lvsae6.gif
A.
Figure 16. Load Transient Response
TPS53129 start18_lvs947.gif
A.
Figure 18. Start-Up Waveforms
TPS53129 effvio18_lvsae6.gif
A.
vO1 = 1.8 V
Figure 20. 1.8-V Efficiency vs Output Current (CH1)
TPS53129 vor18_lvsae6.gif
A.
vO1 = 1.8 V
Figure 22. 1.8-V Output Ripple Voltage
TPS53129 fsw105_lvsae6.gif
A.
IO2 = 3 A
Figure 9. Switching Frequency vs Input Voltage (CH2)
TPS53129 fsw105vio_lvsae6.gif
A.
vO2 = 1.05 V
Figure 11. Switching Frequency vs Output Current (CH2)
TPS53129 vo105vio_lvsae6.gif
A.
VIN = 12 V vO2 = 1.05 V
Figure 13. Output Voltage vs Output Current (CH2)
TPS53129 vovi105_lvsae6.gif
A.
VIN = 12 V vO2 = 1.05 V
Figure 15. Output Voltage vs Input Voltage (CH2)
TPS53129 load105_lvsae6.gif
A.
Figure 17. Load Transient Response
TPS53129 start105_lvs947.gif
A.
Figure 19. Start-Up Waveforms
TPS53129 effvio105_lvsae6.gif
A.
vO2 = 1.05 V
Figure 21. 1.05-V Efficiency vs Output Current (CH2)
TPS53129 vor105_lvsae6.gif
A.
vO2 = 1.05 V
Figure 23. 1.05-V Output Ripple Voltage