SLVS751E November   2007  – January 2024 TPS5430-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information (DDA Package)
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Oscillator Frequency
      2. 6.3.2  Voltage Reference
      3. 6.3.3  Enable (ENA) and Internal Slow Start
      4. 6.3.4  Undervoltage Lockout (UVLO)
      5. 6.3.5  Boost Capacitor (BOOT)
      6. 6.3.6  Output Feedback (VSENSE) and Internal Compensation
      7. 6.3.7  Voltage Feed Forward
      8. 6.3.8  Pulse-Width Modulation (PWM) Control
      9. 6.3.9  Overcurrent Limiting
      10. 6.3.10 Overvoltage Protection (OVP)
      11. 6.3.11 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Operation near Minimum Input Voltage
      2. 6.4.2 Operation with ENA control
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Application Circuit, 12 V to 5 V
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2 Switching Frequency
          3. 7.2.1.2.3 Input Capacitors
          4. 7.2.1.2.4 Output Filter Components
            1. 7.2.1.2.4.1 Inductor Selection
            2. 7.2.1.2.4.2 Capacitor Selection
          5. 7.2.1.2.5 Output Voltage Setpoint
          6. 7.2.1.2.6 Boot Capacitor
          7. 7.2.1.2.7 Catch Diode
          8. 7.2.1.2.8 Advanced Information
            1. 7.2.1.2.8.1 Output Voltage Limitations
            2. 7.2.1.2.8.2 Internal Compensation Network
            3. 7.2.1.2.8.3 Thermal Calculations
        3. 7.2.1.3 Application Curves
      2. 7.2.2 9-V to 21-V Input to 5-V Output Application Circuit
      3. 7.2.3 Circuit Using Ceramic Output Filter Capacitors
        1. 7.2.3.1 Output Filter Component Selection
        2. 7.2.3.2 External Compensation Network
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Layout Guidelines

Connect a low-ESR ceramic bypass capacitor to the VIN pin. Care must be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the ground pin. The best way to do this is to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7-μF ceramic with a X5R or X7R dielectric.

There must be a ground area on the top layer directly underneath the IC, with an exposed area for connection to the thermal pad. Use vias to connect this ground area to any internal ground planes. Use additional vias at the ground side of the input and output filter capacitors as well. The GND pin must be tied to the PCB ground by connecting it to the ground area under the device as shown in Figure 7-12.

The PH pin must be routed to the output inductor, catch diode and boot capacitor. Because the PH connection is the switching node, the inductor must be located very close to PH and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The catch diode must also be placed close to the device to minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component placements and connections shown work well, but other connection routings can also be effective.

Connect the output filter capacitors as shown between the VOUT trace and GND. Keep the loop formed by PH, LOUT, COUT, and GND as small as is practical.

Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not route this trace too close to the PH trace. Due to the size of the IC package and the device pin-out, the trace can need to be routed under the output capacitor. Alternately, the routing can be done on an alternate layer if a trace under the output capacitor is not desired.

If using the grounding scheme shown in Figure 7-12, use a via connection to a different layer to route to the ENA pin.