SLVSDV8 July 2017 TPS54424
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Figure 58 through Figure 61 shows an alternate example PCB layout with unsymmetrical placement of the input capacitors and output capacitors. Both VIN pins are still bypassed to their adjacent PGND pins with an input capacitor placed as close as possible to the IC. When using this alternate layout, CI2 should be increased to 1 µF.