SLUSC70D March   2016  – July 2017 TPS548D22

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 40-A FET
      2. 7.3.2 On-Resistance
      3. 7.3.3 Package Size, Efficiency and Thermal Performance
      4. 7.3.4 Soft-Start Operation
      5. 7.3.5 VDD Supply Undervoltage Lockout (UVLO) Protection
      6. 7.3.6 EN_UVLO Pin Functionality
      7. 7.3.7 Fault Protections
        1. 7.3.7.1 Current Limit (ILIM) Functionality
        2. 7.3.7.2 VDD Undervoltage Lockout (UVLO)
        3. 7.3.7.3 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
        4. 7.3.7.4 Out-of-Bounds Operation
        5. 7.3.7.5 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 DCAP3 Control Topology
      2. 7.4.2 DCAP Control Topology
    5. 7.5 Programming
      1. 7.5.1 Programmable Pin-Strap Settings
        1. 7.5.1.1 Frequency Selection (FSEL) Pin
        2. 7.5.1.2 VSEL Pin
        3. 7.5.1.3 DCAP3 Control and Mode Selection
          1. 7.5.1.3.1 Application Workaround to Support 4-ms and 8-ms SS Settings
      2. 7.5.2 Programmable Analog Configurations
        1. 7.5.2.1 RSP/RSN Remote Sensing Functionality
          1. 7.5.2.1.1 Output Differential Remote Sensing Amplifier
        2. 7.5.2.2 Power Good (PGOOD Pin) Functionality
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 TPS548D22 1.5-V to 16-V Input, 1-V Output, 40-A Converter
      2. 8.2.2 Design Requirements
      3. 8.2.3 Design Procedure
        1. 8.2.3.1  Switching Frequency Selection
        2. 8.2.3.2  Inductor Selection
        3. 8.2.3.3  Output Capacitor Selection
          1. 8.2.3.3.1 Minimum Output Capacitance to Ensure Stability
          2. 8.2.3.3.2 Response to a Load Transient
          3. 8.2.3.3.3 Output Voltage Ripple
        4. 8.2.3.4  Input Capacitor Selection
        5. 8.2.3.5  Bootstrap Capacitor Selection
        6. 8.2.3.6  BP Pin
        7. 8.2.3.7  R-C Snubber and VIN Pin High-Frequency Bypass
        8. 8.2.3.8  Optimize Reference Voltage (VSEL)
        9. 8.2.3.9  MODE Pin Selection
        10. 8.2.3.10 Overcurrent Limit Design.
      4. 8.2.4 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Mounting and Thermal Profile Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

Consider these layout guidelines before starting a layout work using TPS548D22.

  • It is absolutely critical that all GND pins, including AGND (pin 30), DRGND (pin 29), and PGND (pins 13, 14, 15, 16, 17, 18, 19, and 20) are connected directly to the thermal pad underneath the device via traces or plane.
  • Include as many thermal vias as possible to support a 40-A thermal operation. For example, a total of 35 thermal vias are used (outer diameter of 20 mil) in the TPS548D22EVM-784 available for purchase at ti.com. (SLUUBE4)
  • Placed the power components (including input/output capacitors, output inductor and TPS548D22device) on one side of the PCB (solder side). Insert at least two inner layers (or planes) connected to the power ground, in order to shield and isolate the small signal traces from noisy power lines.
  • Place the VIN pin decoupling capacitors as close as possible to the PVIN and PGND pins to minimize the input AC current loop. Place a high-frequency decoupling capacitor (with a value between 1 nF and 0.1 µF) as close to the PVIN pin and PGND pin as the spacing rule allows. This placement helps suppress the switch node ringing.
  • Place VDD and BP decoupling capacitors as close to the device pins as possible. Do not use PVIN plane connection for the VDD pin. Separate the VDD signal from the PVIN signal by using separate trace connections. Provide GND vias for each decoupling capacitor and make the loop as small as possible.
  • Ensure that the PCB trace defined as switch node (which connects the SW pins and up-stream of the output inductor) are as short and wide as possible. In the TPS548D22EVM-784 EVM design, the SW trace width is 200 mil. Use a separate via or trace to connect SW node to snubber and bootstrap capacitor. Do not combine these connections.
  • Place all sensitive analog traces and components (including VOSNS, RSP, RSN, ILIM, MODE, VSEL and FSEL) far away from any high voltage switch node (itself and others), such as SW and BOOT to avoid noise coupling. In addition, place MODE, VSEL and FSEL programming resistors near the device pins.
  • The RSP and RSN pins operate as inputs to a differential remote sense amplifier that operates with very high impedance. It is essential to route the RSP and RSN pins as a pair of diff-traces in Kelvin-sense fashion. Route them directly to either the load sense points (+ and –) or the output bulk capacitors. The internal circuit uses the VOSNS pin for on-time adjustment. It is critical to tie the VOSNS pin directly tied to VOUT (load sense point) for accurate output voltage result.