SLVSAQ8G February   2011  – September 2017 TPS65185

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Data Transmission
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Wake-Up and Power-Up Sequencing
      2. 8.3.2  Dependencies Between Rails
      3. 8.3.3  Soft Start
      4. 8.3.4  Active Discharge
      5. 8.3.5  VPOS/VNEG Supply Tracking
      6. 8.3.6  V3P3 Power Switch
      7. 8.3.7  VCOM Adjustment
        1. 8.3.7.1 Kick-Back Voltage Measurement
        2. 8.3.7.2 Storing the VCOM Power-Up Default Value in Memory
      8. 8.3.8  Fault Handling And Recovery
      9. 8.3.9  Power Good Pin
      10. 8.3.10 Interrupt Pin
      11. 8.3.11 Panel Temperature Monitoring
        1. 8.3.11.1 NTC Bias Circuit
        2. 8.3.11.2 Hot, Cold, and Temperature-Change Interrupts
        3. 8.3.11.3 Typical Application of the Temperature Monitor
    4. 8.4 Device Functional Modes
      1. 8.4.1 SLEEP
      2. 8.4.2 STANDBY
      3. 8.4.3 ACTIVE
      4. 8.4.4 Mode Transitions
        1. 8.4.4.1 SLEEP → ACTIVE
        2. 8.4.4.2 SLEEP → STANDBY
        3. 8.4.4.3 STANDBY → ACTIVE
        4. 8.4.4.4 ACTIVE → STANDBY
        5. 8.4.4.5 STANDBY → SLEEP
        6. 8.4.4.6 ACTIVE → SLEEP
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
    6. 8.6 Register Maps
      1. 8.6.1  Thermistor Readout (TMST_VALUE) Register (address = 0x00h) [reset = N/A]
      2. 8.6.2  Enable (ENABLE) Register (address = 0x01h) [reset = 0h]
      3. 8.6.3  Voltage Adjustment (VADJ) Register (address = 0x02h) [reset = 23h]
      4. 8.6.4  VCOM 1 (VCOM1) Register (address = 0x03h) [reset = 7Dh]
      5. 8.6.5  VCOM 2 (VCOM2) Register (address = 0x04h) [reset = 04h]
      6. 8.6.6  Interrupt Enable 1 (INT_EN1) Register (address = 0x05h) [reset = 7Fh]
      7. 8.6.7  Interrupt Enable 2 (INT_EN2) Register (address = 0x06h) [reset = FFh]
      8. 8.6.8  Interrupt 1 (INT1) Register (address = 0x07h) [reset = 0h]
      9. 8.6.9  Interrupt 2 (INT2) Register (address = 0x08h) [reset = N/A]
      10. 8.6.10 Power-Up Sequence 0 (UPSEQ0) Register (address = 0x09h) [reset = E4h]
      11. 8.6.11 Power-Up Sequence 1 (UPSEQ1) Register (address = 0x0Ah) [reset = 55h]
      12. 8.6.12 Power-Down Sequence 0 (DWNSEQ0) Register (address = 0x0Bh) [reset = 1Eh]
      13. 8.6.13 Power-Down Sequence 1 (DWNSEQ1) Register (address = 0x0Ch) [reset = E0h]
      14. 8.6.14 Thermistor 1 (TMST1) Register (address = 0x0Dh) [reset = 20h]
      15. 8.6.15 Thermistor 2 (TMST2) Register (address = 0x0Eh) [reset = 78h]
      16. 8.6.16 Power Good Status (PG) Register (address = 0x0Fh) [reset = 0h]
      17. 8.6.17 Revision and Version Control (REVID) Register (address = 0x10h) [reset = 45h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RGZ Package and RSL Package
48-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND1 8 — Analog ground for general analog circuitry.
AGND2 48 — Reference point to external thermistor and linearization resistor.
DGND 6 — Digital ground. Connect to ground plane.
INT 2 O Open drain interrupt pin (active low).
INT_LDO 7 O Filter pin for 2.7-V internal supply. Connect a 4.7-µF capacitor from this pin to ground.
N/C 11, 13, 20, 38, 39 — Not internally connected.
PBKG 22 — Die substrate. Connect to the VN pin (–16 V) with a short, wide trace. A wide copper trace improves heat dissipation.
PGND1 41 — Power ground for DCDC1.
PGND2 32 — Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps.
PWR_GOOD 23 O Open-drain power good output pin. Pin is pulled low when one or more rails are disabled or not in regulation. DCDC1, DCDC2, and VCOM have no effect on this pin.(1)
PWRUP 21 I Power-up pin. Pull this pin high to power up all output rails.(1)
SCL 17 I Serial interface (I2C) clock input.
SDA 18 I/O Serial interface (I2C) data input/output.
TS 47 I Thermistor input pin. Connect a 10-kΩ NTC thermistor and a 43-kΩ linearization resistor between this pin and AGND.
V3P3 46 O Output pin of 3.3-V power switch.
VB 42 I Feedback pin for boost converter (DCDC1) and supply for VPOS LDO and VDDH charge pump. Connect a 4.7-µF capacitor from this pin to ground.
VB_SW 40 O Boost converter switch out (DCDC1).
VCOM 15 O Filter pin for panel common-voltage driver. Connect a 4.7-µF capacitor from this pin to ground.
VCOM_CTRL 12 I VCOM enable. Pull this pin high to enable the VCOM amplifier. When pin is pulled low and VN is enabled, VCOM discharge is enabled.(3)
VCOM_DIS 14 I Discharge pin for VCOM. Connect to ground to discharge VCOM to ground whenever VCOM is disabled. Leave floating if discharge function is not desired.
VCOM_PWR 16 I Internal supply input pin to VCOM buffer. Connect to the output of DCDC2, and connect a 4.7-µF capacitor from this pin to ground.
VDDH_D 34 O Base voltage output pin for positive charge pump (CP1). Connect a 100-nF capacitor from this pin to ground.
VDDH_DIS 35 I Discharge pin for VDDH. Connect to VDDH to discharge VDDH to ground whenever the rail is disabled. Leave floating if discharge function is not desired.
VDDH_DRV 36 O Driver output pin for positive charge pump (CP1).
VDDH_FB 33 I Feedback pin for positive charge pump (CP1).
VDDH_IN 37 I Input supply pin for positive charge pump (CP1).
VEE_D 30 O Base voltage output pin for negative charge pump (CP2). Connect a 100-nF capacitor from this pin to ground.
VEE_DIS 29 I Discharge pin for VEE. Connect a resistor from VEE _DIS to VEE to discharge VEE to ground whenever the rail is disabled. Leave floating if discharge function is not desired.
VEE_DRV 28 O Driver output pin for negative charge pump (CP2).
VEE_FB 31 I Feedback pin for negative charge pump (CP2).
VEE_IN 27 I Input supply pin for negative charge pump (CP2) (VEE).
VIN 10 I Input power supply to general circuitry. Connect a 10-µF capacitor from this pin to ground.
VIN3P3 45 I Input pin to 3.3-V power switch.
VIN_P 24 I Input power supply to inverting buck-boost converter (DCDC2). Connect a 10-µF capacitor from this pin to ground.
VN 26 I Feedback pin for inverting buck-boost converter (DCDC2) and supply for VNEG LDO and VEE charge pump. Connect a 4.7-µF capacitor from this pin to ground.
VNEG 3 O Negative supply output pin for panel source drivers. Connect a 4.7-µF capacitor from this pin to ground.
VNEG_DIS 9 O Discharge pin for VNEG. Connect to VNEG to discharge VNEG to ground whenever the rail is disabled. Leave floating if discharge function is not desired.
VNEG_IN 4 I Input pin for LDO2 (VNEG). Connect a 4.7-µF capacitor from this pin to ground.
VN_SW 25 O Inverting buck-boost converter switch out (DCDC2).
VPOS 44 O Positive supply output pin for panel source drivers. Connect a 4.7-µF capacitor from this pin to ground.
VPOS_DIS 19 I Discharge pin for VPOS. Connect a resistor from VPOS_DIS to VPOS to discharge VPOS to ground whenever the rail is disabled. Leave floating if discharge function is not desired.
VPOS_IN 43 I Input pin for LDO1 (VPOS). Connect a 4.7-µF capacitor from this pin to ground.
VREF 1 O Filter pin for 2.25-V internal reference to ADC. Connect a 4.7-µF capacitor from this pin to ground.
WAKEUP 5 I Wake up pin (active high). Pull this pin high to wake up from sleep mode. The device accepts I2C commands after WAKEUP pin is pulled high but power rails remain disabled until PWRUP pin is pulled high.(2)
Thermal Pad — — The thermal pad is internally connected to the PBKG pin. Connect the thermal pad to the VN pin with a short, wide trace. A wide copper trace improves heat dissipation. Do not connect the thermal pad to ground.
(1) There will be 0-ns of deglitch for PWRx.
(2) There will be 93.75-µs of deglitch for WAKEUP.
(3) There will be 62.52-µs of deglitch for VCOM_CTRL.