SLDS234B December 2017 – September 2018 TPS65218D0
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
CONFIG2 is shown in Figure 5-48 and described in Table 5-20.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DC12_RST | UVLOHYS | RESERVED | LS3ILIM | LS2ILIM | |||
R/W-1b | R/W-1b | R-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DC12_RST | R/W | 1b, E2 |
DCDC1 and DCDC2 reset-pin enable 0b = GPIO3 is configured as general-purpose output 1b = GPIO3 is configured as warm-reset input to DCDC1 and DCDC2 |
6 | UVLOHYS | R/W | 1b, E2 |
UVLO hysteresis 0b = 200 mV 1b = 400 mV |
5-4 | RESERVED | R | 0h |
|
3-2 | LS3ILIM | R/W | 0h |
Load switch 3 (LS3) current limit selection 0h = 100 mA, (MIN = 98 mA) 1h = 200 mA, (MIN = 194 mA) 2h = 500 mA, (MIN = 475 mA) 3h = 1000 mA, (MIN = 900 mA) See the LS3 current limit specification in Section 4.5 for more details. |
1-0 | LS2ILIM | R/W | 0h |
Load switch 2 (LS2) current limit selection 0h = 100 mA, (MIN = 94 mA) 1h = 200 mA, (MIN = 188 mA) 2h = 500 mA, (MIN = 465 mA) 3h = 1000 mA, (MIN = 922 mA) See the LS2 current limit specification in Section 4.5 for more details. |