SLDS234B December 2017 – September 2018 TPS65218D0
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
Table 5-6 lists the memory-mapped registers for the TPS65218D0. All register offset addresses not listed in Table 5-6 should be considered as reserved locations and the register contents should not be modified.
SUBADDRESS | ACRONYM | REGISTER NAME | R/W | PASSWORD PROTECTED | SECTION |
---|---|---|---|---|---|
0x0 | CHIPID | CHIP ID | R | No | Go |
0x1 | INT1 | INTERRUPT 1 | R | No | Go |
0x2 | INT2 | INTERRUPT 2 | R | No | Go |
0x3 | INT_MASK1 | INTERRUPT MASK 1 | R/W | No | Go |
0x4 | INT_MASK2 | INTERRUPT MASK 2 | R/W | No | Go |
0x5 | STATUS | STATUS | R | No | Go |
0x6 | CONTROL | CONTROL | R/W | No | Go |
0x7 | FLAG | FLAG | R | No | Go |
0x10 | PASSWORD | PASSWORD | R/W | No | Go |
0x11 | ENABLE1 | ENABLE 1 | R/W | Yes | Go |
0x12 | ENABLE2 | ENABLE 2 | R/W | Yes | Go |
0x13 | CONFIG1 | CONFIGURATION 1 | R/W | Yes | Go |
0x14 | CONFIG2 | CONFIGURATION 2 | R/W | Yes | Go |
0x15 | CONFIG3 | CONFIGURATION 3 | R/W | Yes | Go |
0x16 | DCDC1 | DCDC1 CONTROL | R/W | Yes | Go |
0x17 | DCDC2 | DCDC2 CONTROL | R/W | Yes | Go |
0x18 | DCDC3 | DCDC3 CONTROL | R/W | Yes | Go |
0x19 | DCDC4 | DCDC4 CONTROL | R/W | Yes | Go |
0x1A | SLEW | SLEW RATE CONTROL | R/W | Yes | Go |
0x1B | LDO1 | LDO1 CONTROL | R/W | Yes | Go |
0x20 | SEQ1 | SEQUENCER 1 | R/W | Yes | Go |
0x21 | SEQ2 | SEQUENCER 2 | R/W | Yes | Go |
0x22 | SEQ3 | SEQUENCER 3 | R/W | Yes | Go |
0x23 | SEQ4 | SEQUENCER 4 | R/W | Yes | Go |
0x24 | SEQ5 | SEQUENCER 5 | R/W | Yes | Go |
0x25 | SEQ6 | SEQUENCER 6 | R/W | Yes | Go |
0x26 | SEQ7 | SEQUENCER 7 | R/W | Yes | Go |
Table 5-7 explains the common abbreviations used in this section.
Abbreviation | Description |
---|---|
R | Read |
W | Write |
R/W | Read and write capable |
E2 | Backed by EEPROM |
h | Hexadecimal notation of a group of bits |
b | Hexadecimal notation of a bit or group of bits |
X | Don't care reset value |