SLVSCS9D december   2014  – may 2023 TPS65263-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Enable and Adjusting UVLO
      3. 7.3.3  Soft-Start Time
      4. 7.3.4  Power-Up Sequencing
      5. 7.3.5  V7V Low-Dropout Regulator and Bootstrap
      6. 7.3.6  Out-of-Phase Operation
      7. 7.3.7  Output Overvoltage Protection (OVP)
      8. 7.3.8  PSM
      9. 7.3.9  Slope Compensation
      10. 7.3.10 Overcurrent Protection
        1. 7.3.10.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.10.2 Low-Side MOSFET Overcurrent Protection
      11. 7.3.11 Power Good
        1. 7.3.11.1 Adjustable Switching Frequency
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface Description
      2. 7.4.2 I2C Update Sequence
    5. 7.5 Register Maps
      1. 7.5.1 VOUT2_SEL: Vout2 Voltage Selection Register (Address = 0x01H)
      2. 7.5.2 VOUT1_COM: Buck1 Command Register (offset = 0x03H)
      3. 7.5.3 VOUT2_COM: Buck2 Command Register (offset = 0x04H)
      4. 7.5.4 VOUT3_COM: Buck3 Command Register (offset = 0x05H)
      5. 7.5.5 SYS_STATUS: System Status Register (offset = 0x06H)
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Loop Compensation
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

VIN = 12 V, FSW = 500 kHz, TJ = –40°C to 125°C, typical values are at TJ = 25°C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT SUPPLY VOLTAGE
VINInput voltage range418V
UVLOVIN UVLOVIN rising3.53.84V
VIN falling3.13.33.5V
Hysteresis500mV
IDDSDNShutdown supply currentEN1 = EN2 = EN3 = 0 V49.518µA
IDDQ_NSWInput quiescent current without buck1/2/3 switchingEN1 = EN2 = EN3 = 5 V, FB1 = FB2 = FB3 = 0.8 V5507801150µA
IDDQ_NSW1EN1 = 5 V, EN2 = EN3 = 0 V, FB1 = 0.8 V180370590µA
IDDQ_NSW2EN2 = 5 V, EN1 = EN3 = 0 V, FB2 = 0.8V180370590µA
IDDQ_NSW3EN3 = 5 V, EN1 = EN2 = 0 V, FB3 = 0.8 V180370590µA
V7VV7V LDO output voltageV7V load current = 0 A6.3V
IOCP_V7VV7V LDO current limit78185260mA
FEEDBACK VOLTAGE REFERENCE
VFBFeedback voltageVCOMP = 1.2 V0.5940.60.606V
BUCK1, BUCK2, BUCK3
VENXHEN1/2/3 high-level input voltage1.121.21.26V
VENXLEN1/2/3 low-level input voltage1.051.151.21V
IENX1EN1/2/3 pullup currentENx = 1 V2.53.95.9µA
IENX2EN1/2/3 pullup currentENx = 1.5 V5.16.99.2µA
IENhysHysteresis current2.633.3µA
ISSXSoft-start charging current3.95.26.5µA
tON_MINMinimum on-time5075110ns
Gm_EAError amplifier transconductance–2 µA < ICOMPX < 2 µA140300450µs
Gm_PS1/2/3COMP1/2/3 voltage to inductor current Gm(1)ILX = 0.5 A7.4A/V
ILIMIT1Buck1 peak inductor current limit4.35.46.5A
ILIMITSINK1Buck1 low-side sink current limit0.71.31.8A
ILIMIT2/3Buck2/buck3 peak inductor current limit2.553.33.9A
ILIMITSINK2/3Buck2/buck3 low-side sink current limit0.511.4A
Rdson_HS1Buck1 high-side switch resistanceVIN = 12 V105
Rdson_LS1Buck1 low-side switch resistanceVIN = 12 V65
Rdson_HS2Buck2 high-side switch resistanceVIN = 12 V140
Rdson_LS2Buck2 low-side switch resistanceVIN = 12 V90
Rdson_HS3Buck3 high-side switch resistanceVIN = 12 V140
Rdson_LS3Buck3 low-side switch resistanceVIN = 12 V90
HICCUP TIMING
tHiccup_waitOvercurrent wait time(1)256cycles
tHiccup_reHiccup time before restart(1)8192cycles
POWER GOOD
Vth_PGFeedback voltage thresholdFBx undervoltage falling92.5%VREF
FBx undervoltage rising95
FBx overvoltage rising107.5
FBx overvoltage falling105
tDEGLITCH(PG)_FPGOOD falling edge deglitch time112cycles
tRDEGLITCH(PG)_RPGOOD rising edge deglitch time616cycles
IPGPGOOD pin leakage0.1µA
VLOW_PGPGOOD pin low voltageISINK = 1 mA0.4V
OSCILLATOR
FSWSwitching frequencyROSC = 88.7 kΩ430500560kHz
FSW_rangeSwitching frequency2002300kHz
TSYNC_wClock sync minimum pulse width80ns
FSYNC_HIClock sync high threshold2V
VSYNC_LOClock sync low threshold0.4V
FSYNCClock sync frequency range2002300kHz
THERMAL PROTECTION
TTRIP_OTPThermal protection trip point(1)Temperature rising160°C
THYST_OTPHysteresis20°C
I2C INTERFACE
AddrAddress(2)0x60H
VIH SDA,SCLInput high voltage2V
VIL SDA,SCLInput low voltage0.4V
IIInput currentSDA, SCL, VI = 0.4 to 4.5 V–1010µA
VOL SDASDA output low voltageSDA open drain, IOL = 4 mA0.4V
ƒ(SCL)Maximum SCL clock frequency(2)400kHz
tBUFBus free time between a STOP and START condition(2)1.3µs
tHD_STAHold time (repeated) START condition(2)0.6µs
tSU_STOSetup time for STOP condition(2)0.6µs
tLOWLow period of the SCL clock(2)1.3µs
tHIGHHigh period of the SCL clock(2)0.6µs
tSU_STASetup time for a repeated START condition(2)0.6µs
tSU_DATData setup time(2)0.1µs
tHD_DATData hold time(2)00.9µs
tRCLRise time of SCL signal(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
tRCL1Rise time of SCL signal after a repeated START condition and after an acknowledge bit(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
tFCLFall time of SCL signal(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
tRDARise time of SDA signal(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
tFDAFall time of SDA signal(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
CBCapacitance of bus line(SCL and SDA)(2)400pF
Lab validation result
Not production tested