SLVSDA6 October   2016 TPS65266-1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Enable and Adjusting UVLO
      3. 7.3.3  Soft-Start Time
      4. 7.3.4  Power-Up Sequencing
      5. 7.3.5  Bootstrap Voltage and BST-LX UVLO
      6. 7.3.6  Out of Phase Operation
      7. 7.3.7  Output Overvoltage Protection (OVP)
      8. 7.3.8  Slope Compensation
      9. 7.3.9  Overcurrent Protection
        1. 7.3.9.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.9.2 Low-Side MOSFET Overcurrent Protection
      10. 7.3.10 Power Good
      11. 7.3.11 Adjustable Switching Frequency
      12. 7.3.12 PSM
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 2.6 V (Minimum VIN)
      2. 7.4.2 Operation With EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Loop Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Related Parts
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The device is a triple-synchronous step-down DC/DC converter. It is typically used to convert a higher DC voltage to lower DC voltages with a continuously available output current of 3 A/2 A/2 A. The following design procedure can be used to select component values for the TPS65266-1. This section presents a simplified discussion of the design process.

8.2 Typical Application

TPS65266-1 typ_app_LVSCT9.gif Figure 33. Typical Application Schematic

8.2.1 Design Requirements

This example details the design of a triple-synchronous step-down converter. The designer must know a few parameters to start the design process. These parameters are typically determined at the system level. For this example, start with the following known parameters in Table 2.

Table 2. Design Parameters

Parameter Value
Vout1 1.0 V
Iout1 3 A
Vout2 1.5 V
Iout2 2 A
Vout3 1.8 V
Iout3 2 A
Transient response 1-A load step ±5%
Input voltage 5.0 V normal, 2.7 to 6 V
Output voltage ripple ±1%
Switching frequency 1 MHz

8.2.2 Detailed Design Procedure

8.2.2.1 Output Inductor Selection

To calculate the value of the output inductor, use Equation 8. LIR is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for the majority of applications.

Equation 8. TPS65266-1 eq_08_LVSCT9.gif

For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 10 and Equation 11.

Equation 9. TPS65266-1 eq_09_LVSCT9.gif
Equation 10. TPS65266-1 eq_10_LVSCT9.gif
Equation 11. TPS65266-1 eq_11_LVSCT9.gif

The current flowing through the inductor is the inductor ripple current plus the output current. During power-up, faults, or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated previously. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current.

8.2.2.2 Output Capacitor Selection

The three primary considerations for selecting the value of the output capacitor are: the output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance must be selected based on the most stringent of these three criteria.

The first criterion is the desired response to a large change in the load current. The output capacitor needs to supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 12 shows the minimum output capacitance necessary to accomplish this.

Equation 12. TPS65266-1 eq_12_LVSCT9.gif

where

  • ΔIout is the change in output current.
  • ƒSW is the regulator's switching frequency.
  • ΔVout is the allowable change in the output voltage.

Equation 13 calculates the minimum output capacitance needed to meet the output voltage ripple specification.

Equation 13. TPS65266-1 eq_13_LVSCT9.gif

where

  • ƒSW is the switching frequency.
  • Vripple is the maximum allowable output voltage ripple.
  • Iripple is the inductor ripple current.

Equation 14 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification.

Equation 14. TPS65266-1 eq_14_LVSCT9.gif

Additional capacitance deratings for aging, temperature, and DC bias should be factored in, which increase this minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Equation 15 can be used to calculate the RMS ripple current the output capacitor needs to support.

Equation 15. TPS65266-1 eq_15_LVSCT9.gif

8.2.2.3 Input Capacitor Selection

The TPS65266-1 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 μF of effective capacitance on the VIN input voltage pins. In some applications, additional bulk capacitance may also be required for the VIN input. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS65266-1. Calculate the input ripple current using Equation 16.

Equation 16. TPS65266-1 eq_16_LVSCT9.gif

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. The input capacitance value determines the input ripple voltage of the regulator. Calculate the input voltage ripple using Equation 17.

Equation 17. TPS65266-1 eq_17_LVSCT9.gif

8.2.2.4 Loop Compensation

The TPS65266-1 incorporates a peak current mode control scheme. The error amplifier is a transconductance amplifier with a gain of 290 µS. A typical type II compensation circuit adequately delivers a phase margin between 30° and 90°. Cb adds a high-frequency pole to attenuate high-frequency noise when needed. To calculate the external compensation components, follow these steps.

  1. Select switching frequency, ƒSW, that is appropriate for application depending on L and C sizes, output ripple, EMI, and so forth. Switching frequency between 500 kHz to 1.5 MHz gives best trade-off between performance and cost. To optimize efficiency, lower switching frequency is desired.
  2. Set up crossover frequency, ƒc, which is typically between 1 / 5 and 1 / 20 of ƒSW.
  3. RC can be determined by:
    4. Equation 18. TPS65266-1 eq_18_LVSCT9.gif

    where

    • Gm_EA is the error amplifier gain (290 µS).
    • Gm_PS is the power stage voltage to current conversion gain (10 A/V).
  4. Calculate CC by placing a compensation zero at or before the dominant pole TPS65266-1 eq_19_LVSCT9.gif
    5. Equation 19. TPS65266-1 eq_20_LVSCT9.gif
  5. Optional Cb can be used to cancel the zero from the ESR associated with CO.
    6. Equation 20. TPS65266-1 eq_21_LVSCT9.gif
  6. Type III compensation can be implemented with the addition of one capacitor, C1. This allows for slightly higher loop bandwidths and higher phase margins. If used, C1 is calculated from Equation 21.
    7. Equation 21. TPS65266-1 eq_22_C1_LVSCT9.gif
TPS65266-1 DC_loop_comp_LVSCT9.gif Figure 34. DC/DC Loop Compensation

8.2.3 Application Curves

TPS65266-1 app_01_LVSCT9.gif
Figure 35. Buck1, Soft-Start, Iout = 3 A
TPS65266-1 app_02_LVSCT9.gif
Figure 36. Buck2, Soft-Start, Iout = 2 A
TPS65266-1 app_03_LVSCT9.gif
Figure 37. Buck3, Soft-Start, Iout = 2 A
TPS65266-1 app_05_LVSCT9.gif
Figure 39. Buck2, Output Voltage Ripple, Iout = 2 A
TPS65266-1 app_07_LVSCT9.gif
SR = 0.25 A/µs
Figure 41. Buck1, Load Transient, 0.75 to 1.5 A
TPS65266-1 app_09_LVSCT9.gif
SR = 0.25 A/µs
Figure 43. Buck2, Load Transient, 0.5 to 1.0 A
TPS65266-1 app_11_LVSCT9.gif
SR = 0.25 A/µs
Figure 45. Buck3, Load Transient, 0.5 to 1.0 A
TPS65266-1 app_13_LVSCT9.gif
Figure 47. Buck1, Hiccup and Recovery
TPS65266-1 app_15_LVSCT9.gif
Figure 49. Buck3, Hiccup and Recovery
TPS65266-1 app_04_LVSCT9.gif
Figure 38. Buck1, Output Voltage Ripple, Iout = 3 A
TPS65266-1 app_06_LVSCT9.gif
Figure 40. Buck3, Output Voltage Ripple, Iout = 2 A
TPS65266-1 app_08_LVSCT9.gif
SR = 0.25 A/µs
Figure 42. Buck1, Load Transient, 1.5 to 2.25 A
TPS65266-1 app_10_LVSCT9.gif
SR = 0.25 A/µs
Figure 44. Buck2, Load Transient, 1.0 to 1.5 A
TPS65266-1 app_12_LVSCT9.gif
SR = 0.25 A/µs
Figure 46. Buck3, Load Transient, 1.0 to 1.5 A
TPS65266-1 app_14_LVSCT9.gif
Figure 48. Buck2, Hiccup and Recovery
TPS65266-1 app_16_LVSCT9.gif
Figure 50. 180° Out of Phase