SLVSDA6 October   2016 TPS65266-1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Enable and Adjusting UVLO
      3. 7.3.3  Soft-Start Time
      4. 7.3.4  Power-Up Sequencing
      5. 7.3.5  Bootstrap Voltage and BST-LX UVLO
      6. 7.3.6  Out of Phase Operation
      7. 7.3.7  Output Overvoltage Protection (OVP)
      8. 7.3.8  Slope Compensation
      9. 7.3.9  Overcurrent Protection
        1. 7.3.9.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.9.2 Low-Side MOSFET Overcurrent Protection
      10. 7.3.10 Power Good
      11. 7.3.11 Adjustable Switching Frequency
      12. 7.3.12 PSM
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 2.6 V (Minimum VIN)
      2. 7.4.2 Operation With EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Inductor Selection
        2. 8.2.2.2 Output Capacitor Selection
        3. 8.2.2.3 Input Capacitor Selection
        4. 8.2.2.4 Loop Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Related Parts
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) (1)
MIN MAX UNIT
Voltage at VIN1, VIN2, VIN3, VINQ –0.3 7 V
LX1, LX2, LX3 (maximum withstand voltage transient <20 ns) –1.0 7
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively –0.3 7
EN1, EN2, EN3, PGOOD –0.3 7
FB1, FB2, FB3, COMP1 , COMP2, COMP3, SS1, SS2, SS3, ROSC –0.3 3.6
AGND, PGND1, PGND2, PGND3 –0.3 0.3
TJ Operating junction temperature –30 125 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Voltage at VIN1, VIN2, VIN3, VINQ 2.7 6 V
LX1, LX2, LX3 (maximum withstand voltage transient <20 ns) –0.8 6
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively –0.1 6
EN1, EN2, EN3, PGOOD –0.1 6
FB1, FB2, FB3, COMP1 , COMP2, COMP3, SS1, SS2, SS3, ROSC –0.1 3
TJ Operating junction temperature –30 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS65266-1 UNIT
RHB
32-PIN VQFN
RθJA Junction-to-ambient thermal resistance 34.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 27.5 °C/W
RθJB Junction-to-board thermal resistance 8.3 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 8.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.8 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TJ = –30°C to 125°C, VIN= 5 V, typical values are at TJ = 25°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY VOLTAGE
VIN Input voltage range 2.7 6 V
UVLO VIN undervoltage lockout VIN rising 2.35 2.45 2.6 V
VIN falling 2.15 2.25 2.37 V
IDD(SDN) Shutdown supply current EN1 = EN2 = EN3 = 0 V 9 µA
IDD(Q_NSW) Input quiescent current without buck1/2/3 switching EN1 = EN2 = EN3 = 5 V,
FB1 = FB2 = FB3 = 0.8 V		 790 µA
IDD(Q_NSW1) EN1 = 5 V, EN2 = EN3 = 0 V,
FB1 = 0.8 V		 340 µA
IDD(Q_NSW2) EN2 = 5 V, EN1 = EN3 = 0 V,
FB2 = 0.8 V		 340 µA
IDD(Q_NSW3) EN3 = 5 V, EN1 = EN2 = 0 V,
FB3 = 0.8 V		 340 µA
BUCK1, BUCK2, BUCK3
VFB Feedback voltage VCOMP = 1.2 V 0.594 0.6 0.606 V
VEN(XH) EN1/2/3 high-level input voltage 1.2 1.26 V
VEN(XL) EN1/2/3 low-level input voltage 1.1 1.15 V
IEN(X1) EN1/2/3 pullup current ENx = 1 V 1.7 2.1 2.5 µA
IEN(X2) EN1/2/3 pullup current ENx = 1.3 V 5.3 µA
IEN(hys) Hysteresis current 3.2 µA
ISSX Soft-start charging current 4.5 5.5 6.5 µA
G(m_PS1/2/3) COMP1/2/3 voltage to inductor current Gm(2) ILX = 0.5 A 10 A/V
I(LIMIT1) Buck1 peak inductor current limit 3.55 4.6 5.6 A
I(LIMITSINK1) Buck1 low-side sink current limit 1.4
I(LIMIT2/3) Buck2/3 peak inductor current limit 2.35 3.1 3.7 A
I(LIMITSINK2/3) Buck2/3 low-side sink current limit 1.2 A
Rds(on)_HS1 Buck1 high-side switch resistance(1) VINQ = 5 V 45 mΩ
Rds(on)_LS1 Buck1 low-side switch resistance(1) VINQ = 5 V 50 mΩ
Rds(on)_HS2 Buck2 high-side switch resistance(1) VINQ = 5 V 60 mΩ
Rds(on)_LS2 Buck2 low-side switch resistance(1) VINQ = 5 V 60 mΩ
Rds(on)_HS3 Buck3 high-side switch resistance(1) VINQ = 5 V 60 mΩ
Rds(on)_LS3 Buck3 low-side switch resistance(1) VINQ = 5 V 60 mΩ
POWER GOOD
V(th_PG) Feedback voltage threshold FBx undervoltage falling 92.5 %VREF
FBx undervoltage rising 95 %VREF
IPG PGOOD pin leakage 1 µA
V(LOW_PG) PGOOD pin low voltage I(SINK) = 1 mA 0.4 V
OSCILLATOR
FSW Switching frequency R(OSC) = 51.1 kΩ 920 1000 1080 kHz
FSW(range) Switching frequency 250 2400 kHz
F(SYNC) Clock sync frequency range 250 2400 kHz
F(SYNC_HI) Clock sync high threshold 2 V
V(SYNC_LO) Clock sync low threshold 0.4 V
THERMAL PROTECTION
T(TRIP_OTP)(2) Thermal protection trip point Temperature rising 160 °C
T(HYST_OTP)(2) Hysteresis 20 °C
(1) Typical value without bonding wires; from design simulation
(2) Lab validation result

6.6 Timing Requirements

MIN NOM MAX UNIT
BUCK1, BUCK2, BUCK3
tON_MIN Minimum on-time 80 115 ns
Gm_EA Error amplifier transconductance –2 µA < I(COMPX) < 2 µA 290 µS
HICCUP TIMING
tHiccup_wait Overcurrent wait time(2) 512 cycles
tHiccup_re Hiccup time before restart(2) 16382 cycles
POWER GOOD
tDEGLITCH(PG)_F PGOOD falling edge deglitch time 128 cycles
tRDEGLITCH(PG)_R PGOOD rising edge deglitch time 16350 cycles
OSCILLATOR
tSYNC_w Clock sync minimum pulse duration 80 ns

6.7 Typical Characteristics

TA = 25°C, VIN = 5 V, VOUT1 = 1.0 V, VOUT2 = 1.5 V, VOUT3 = 1.8 V FSW = 1 MHz (unless otherwise noted)
TPS65266-1 D002_SLVSDA6.gif
Figure 1. Buck1 Efficiency
TPS65266-1 D004_SLVSDA6.gif
Figure 3. Buck3 Efficiency
TPS65266-1 D005_SLVSCT9.gif
Figure 5. Buck2, Load Regulation
TPS65266-1 D007_SLVSDA6.gif
Figure 7. Buck1, Line Regulation
TPS65266-1 D009_SLVSDA6.gif
Figure 9. Buck3, Line Regulation
TPS65266-1 D011_SLVSDA6.gif
ROSC = 51.1 kΩ
Figure 11. Oscillator Frequency vs Temperature
TPS65266-1 D013_SLVSDA6.gif
VIN = 5 V EN = 1 V
Figure 13. EN Pin Pullup Current vs Temperature, EN = 1 V
TPS65266-1 D015_SLVSDA6.gif
VIN = 5 V
Figure 15. EN Pin Threshold Rising vs Temperature
TPS65266-1 D017_SLVSDA6.gif
VIN = 5 V
Figure 17. SS Pin Charge Current vs Temperature
TPS65266-1 D019_SLVSDA6.gif
VIN = 5 V
Figure 19. Buck2 High-Side Current Limit vs Temperature
TPS65266-1 D003_SLVSDA6.gif
Figure 2. Buck2 Efficiency
TPS65266-1 D004_SLVSCT9.gif
Figure 4. Buck1, Load Regulation
TPS65266-1 D006_SLVSCT9.gif
Figure 6. Buck3, Load Regulation
TPS65266-1 D008_SLVSDA6.gif
Figure 8. Buck2, Line Regulation
TPS65266-1 D010_SLVSDA6.gif
Figure 10. Voltage Reference vs Temperature
TPS65266-1 D012_SLVSDA6.gif
VIN = 5 V
Figure 12. Shutdown Quiescent Current vs Temperature
TPS65266-1 D014_SLVSDA6.gif
VIN = 5 V EN = 1.3 V
Figure 14. EN Pin Pullup Current vs Temperature, EN = 1.3 V
TPS65266-1 D016_SLVSDA6.gif
VIN = 5 V
Figure 16. EN Pin Threshold Falling vs Temperature
TPS65266-1 D018_SLVSDA6.gif
VIN = 5 V
Figure 18. Buck1 High-Side Current Limit vs Temperature
TPS65266-1 D020_SLVSDA6.gif
VIN = 5 V
Figure 20. Buck3 High-Side Current Limit vs Temperature