SGLS303F May   2005  – April 2016 TPS732-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Shutdown
      3. 7.3.3 Dropout Voltage
      4. 7.3.4 Transient Response
      5. 7.3.5 Reverse Current
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input and Output Capacitor Requirements
        2. 8.2.2.2 Output Noise
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation
    4. 10.4 Package Mounting
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS732-Q1 belongs to a family of new generation LDO regulators that use an NMOS pass transistor to achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints. These features, combined with low noise and an enable input, make the TPS732-Q1 family of devices ideal for portable applications. This regulator family offers a wide selection of fixed output voltage versions and an adjustable output version. All versions have thermal and overcurrent protection, including foldback current limit.

8.2 Typical Application

Figure 29 shows the basic circuit connections for the fixed voltage models. Figure 30 gives the connections for the adjustable output version (TPS73201-Q1).

TPS732-Q1 ta_cir_fxd_v_gls303.gif Figure 29. Typical Application Circuit for Fixed-Voltage Versions
TPS732-Q1 ta_cir_adj_gls303.gif Figure 30. Typical Application Circuit for Adjustable-Voltage Versions

8.2.1 Design Requirements

R1 and R2 can be calculated for any output voltage using the formula shown in Figure 30. Sample resistor values for common output voltages are shown in Figure 31. For best accuracy, make the parallel combination of R1 and R2 approximately 19 kΩ.

TPS732-Q1 bd2_gls303.gif
VOUT = ( R1 + R2 ) / R2 × 1.204
R1 || R2 ≅ 19 kΩ for best accuracy.
Figure 31. Adjustable Voltage Version

Table 1. Standard 1% Resistor Values for Common Output Voltages

VOUT R1 R2
1.2 V Short Open
1.5 V 23.2 kW 95.3 kW
1.8 V 28 kW 56.2 kW
2.5 V 39.2 kW 36.5 kW
2.8 V 44.2 kW 33.2 kW
3 V 46.4 kW 30.9 kW
3.3 V 52.3 kW 30.1 kW
5 V 78.7 kW 24.9 kW

8.2.2 Detailed Design Procedure

8.2.2.1 Input and Output Capacitor Requirements

Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1‑μF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or the device is located several inches from the power source.

The TPS732-Q1 family of devices does not require an output capacitor for stability and has maximum phase margin with no capacitor. It is designed to be stable for all available types and values of capacitors. In applications where VIN – VOUT < 0.5 V and multiple low ESR capacitors are in parallel, ringing may occur when the product of COUT and total ESR drops below 50 nF. Total ESR includes all parasitic resistances, including capacitor ESR and board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance will meet this requirement.

8.2.2.2 Output Noise

A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the dominant noise source within the TPS732-Q1 family of devices and it generates approximately 32 μVRMS (10 Hz to 100 kHz) at the reference output (NR). The regulator control loop gains up the reference noise with the same gain as the reference voltage, so that the noise voltage of the regulator is approximately given by:

Equation 3. TPS732-Q1 Q_vn32_gls303.gif

Because the value of VREF is 1.2 V, this relationship reduces to:

Equation 4. TPS732-Q1 Q_vn27_gls303.gif

where

  • CNR does not exist

An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF, the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of approximately 3.2, giving the approximate relationship:

Equation 5. TPS732-Q1 Q_vn85_gls303.gif

where

  • CNR = 10 nF

This noise reduction effect is shown as RMS Noise Voltage vs CNR in Typical Characteristics.

The TPS73201-Q1 adjustable version does not have the noise-reduction pin available. However, connecting a feedback capacitor, CFB, from the output to the FB pin will reduce output noise and improve load transient performance.

The TPS732-Q1 family of devices uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of the NMOS pass element above VOUT. The charge pump generates approximately 250 μV of switching noise at approximately 2 MHz; however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and COUT.

8.2.3 Application Curves

TPS732-Q1 app_poweron_sgls303.gif Figure 32. Start-Up
TPS732-Q1 app_poweroff_sgls303.gif Figure 33. Shutdown