SBVS425A december   2022  – may 2023 TPS748A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics: IOUT = 50 mA
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable and Shutdown
      2. 7.3.2 Active Discharge
      3. 7.3.3 Power-Good Output (PG)
      4. 7.3.4 Internal Current Limit
      5. 7.3.5 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input, Output, and Bias Capacitor Requirements
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Output Noise
      4. 8.1.4 Estimating Junction Temperature
      5. 8.1.5 Soft Start, Sequencing, and Inrush Current
      6. 8.1.6 Power-Good Operation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-4C75B409-3522-49D8-B7A8-5A8706C2A3EA-low.gif Figure 5-1 DRC Package,10-Pin VSON With Thermal Pad(Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME VSON
BIAS 4 I Bias input voltage for the error amplifier, reference, and internal control circuits. Use a 1-µF or larger input capacitor for optimal performance. If IN is connected to BIAS, a 4.7-µF or larger capacitor must be used.
EN 5 I Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left unconnected.
FB 8 I Feedback pin. This pin is the feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating.
GND 6 — Ground
IN 1, 2 I Input to the device. Use a 1-µF or larger input capacitor for optimal performance.
NC N/A — No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane.
OUT 9, 10 O Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2 μF, ceramic) is needed from this pin to ground to assure stability.
PG 3 O Power-good pin. An open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a low-impedance state. Connect a pullup resistor (10 kΩ to 1 MΩ) from this pin to a supply of up to 6.0 V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left unconnected if output monitoring is not necessary.
SS 7 — Soft-start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left unconnected, the regulator output soft-start ramp time is typically 200 μs.
Thermal pad — Must be soldered to the ground plane for increased thermal performance. Internally connected to ground.