SLVSAA0E November   2010  – March 2020 TPS7A6201-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Regulator Stability
      2.      Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Up
      2. 7.3.2 Adjustable Output Voltage
      3. 7.3.3 Enable Input
      4. 7.3.4 Charge Pump Operation
      5. 7.3.5 Undervoltage Shutdown
      6. 7.3.6 Low Voltage Tracking
      7. 7.3.7 Integrated Fault Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Power Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
        3. 8.2.2.3 Feedback Resistor
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Dissipation and Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • KTT|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

KTT Package
5-Pin TO-263
Top View
TPS7A6201-Q1 pinout_ktt5_lvsaa0.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 VIN I Input voltage pin: The unregulated input voltage is supplied to this pin. A bypass capacitor shall be connected between VIN pin and GND pin to dampen input line transients.
2 EN I Enable pin: This is a high voltage tolerant input pin with an internal pulldown. A high input to this pin activates the device and turns the regulator ON. This input can be connected to VIN terminal for self bias applications. If this pin is not connected, the device stays disabled.
3 GND I/O Ground pin: This is signal ground pin of the IC.
4 FB I Feedback pin: This pin is used to connect external resistors to ground to program the output voltage.
5 VOUT O Regulated output voltage pin: This is a regulated output voltage pin with a limitation on maximum output current. An external resistor divider is connected at this pin to program the output voltage. To achieve stable operation and prevent oscillation, an external output capacitor (COUT) with low ESR shall be connected between this pin and GND pin.